PDF RTM660-107R Data sheet ( Hoja de datos )

Número de pieza	RTM660-107R
Descripción	Clock Generator
Fabricantes	RealTek
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No Preview Available ! Clock Generator General Description The RTM660-107R is a single chip frequency generator for VIA P4X266 with INTEL P4 Clock Synthesizer Driver Specification. The clock chip provides standard serial bus for programming device function. Base on the function above, the spread spectrum can be enable for reducing EMI. Features ! ! ! ! ! ! ! ! ! ! ! ! ! ! Support Up to 266 MHz frequency. Power Down feature. Programmable Spread Spectrum depth. Programmable Spread Spectrum model. Programmable driving strength. Programmable skew delay. Programmable PLL frequency. Programmable Loop Filter. Programmable Smooth-Divider. Programmable current Iref. Programmable current Vg( Vref). Programmable Watch Dog & Smooth Reset circuit. DOS/WIN9x/WIN2000/WINNT AP. Enhance 266/233/200/166/133/100/66 CPU frequency ratio. FS4/REF 0 VDD_3.3 GND X1 X2 VDD_3.3 FS3/48Mhz FS2/24_48#Mhz GND FS0/PCI - F FS1/PCI - 0 Mult/PCI - 1 GND FS5*/PCI - 2 ENWD#/PCI - 3 VDD_3.3 PCI - 4 PCI - 5 PCI - 6 GND PCI - 7 PD#* AGP - 0 VDD_3.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 VDD_2.5 47 GND 46 IOAPIC - 0 45 IOAPIC - 1 44 GND 43 VDD_2.5 42 CPU - CS 41 CPU - CS# 40 CPU - 0 39 CPU - 0# 38 VDD_3.3 37 Iref 36 GND 35 CPU - 1 34 CPU - 1# 33 Vtt_Power_Good# 32 CPU_Stop#* 31 PCI_Stop#* 30 RESET# 29 SDATA 28 SCLK 27 AGP - 2 26 AGP - 1 25 GND Sdata Sclk WDEN# FS0..FS5 Mult0 standard serial bus ROM CPU stop# PCI stop# PD# PWRGD# Digital control XTAL PLL2 PLL1 Current PAD CPU0..2 CPU#0..2 IREF Divider & Muxer Delay & Stop Buffer & Strength control REF PCIF PCI0..7 IOAPIC 0:1 AGP 0:2 CPU T:C RESET# 24_48 MHz 48MHz 02/01/06 -1- 1 page Register Description Clock Generator CR 00h Bit Bit7 Bit6 Bit5=0 Bit4 Bit3 Bit2 Bit1 Bit0 Description 0 = frequency is selected by latched input FS[5:0] 1 = frequency is selected by CR00h – bit 5, 4, 3, 2, 1, 0 0 = spread spectrum disable 1 = spread spectrum enable Bit4 Bit3 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Bit2 Bit1 Bit0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 CPU 102.00 105.00 108.00 111.00 114.00 117.00 120.00 123.00 126.00 130.00 136.00 140.00 144.00 148.00 152.00 156.00 160.00 164.00 166.60 170.00 175.00 180.00 185.00 190.00 66.80 100.90 200.40 133.90 66.00 100.00 200.00 133.00 Ratio 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.50 2.50 2.50 2.50 2.50 2.50 1.00 1.50 3.00 2.00 1.00 1.50 3.00 2.00 Note1: Default at power-up will be for latched logic inputs to define frequency, Bit 5:0 are default to 000000. 3V66 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 84.00 86.67 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 66.64 68.00 70.00 72.00 74.00 76.00 66.80 67.27 66.80 66.95 66.00 66.67 66.67 66.50 Default 0 0 PCI 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.33 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 33.32 34.00 35.00 36.00 37.00 38.00 33.40 33.63 33.40 33.48 33.00 33.33 33.33 33.25 0 0 0 0 0 0 02/01/06 -5- 5 Page Clock Generator Power Down Function PD# CPU 0 Iref*2 1 On CPU# float On AGP Low On PCI-F PCI REF 48 24/48 Osc VCOs Itotal Low Low Low Low Low Off Off 25/45 mA On On On On On On On 280 mA Power Down Waveform 10 ns PD# CPU 100MHz CPU# 100MHz 3V66 66MHz 3V66_Buf 66MHz PCI 33MHz REF 14.318MHz 48MHz 48MHz posedge 1 posedge 2 waiting posedge & negedge negedge 1 posedge 1 negedge 1 posedge 1 negedge 1 posedge 1 negedge 1 posedge 1 posedge 1 negedge 1 negedge 1 Note 1. After PD# is sampled active (Low) for 2 consecutive rising edges of CPUCLK#, all the output clocks are driven Low on their next High to Low transition. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 02/01/06 - 11 - 11 Page

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