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GS881Z18CD の電気的特性と機能

GS881Z18CDのメーカーはGSI Technologyです、この部品の機能は「9Mb Pipelined and Flow Through Synchronous NBT SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS881Z18CD
部品説明 9Mb Pipelined and Flow Through Synchronous NBT SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS881Z18CD Datasheet, GS881Z18CD PDF,ピン配置, 機能
GS881Z18/32/36C(T/D)-xxx
100-Pin TQFP & 165-Bump BGA 9Mb Pipelined and Flow Through
Commercial Temp
Synchronous NBT SRAM
333 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Functional Description
The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D)
is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D)
is implemented with GSI's high performance CMOS
technology and is available in a JEDEC-standard 100-pin
TQFP package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-333 -300 -250 -200 -150 Unit
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5 2.5 2.5 3.0 3.8 ns
3.0 3.3 4.0 5.0 6.7 ns
240 225 195 170 140 mA
280 260 225 195 160 mA
4.5 5.0 5.5 6.5 7.5 ns
4.5 5.0 5.5 6.5 7.5 ns
180 165 160 140 128 mA
205 190 180 160 145 mA
Rev: 1.04 7/2012
1/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 Page





GS881Z18CD pdf, ピン配列
GS881Z18/32/36C(T/D)-xxx
GS881Z32CT 100-Pin TQFP Pinout (Package T)
NC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD2
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
256K x 32
72
71
11 Top View
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
NC
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.04 7/2012
3/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


3Pages


GS881Z18CD 電子部品, 半導体
GS881Z18/32/36C(T/D)-xxx
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 CKE ADV A17 A A
A
B NC A E2 NC BA CK W G NC A NC B
C
NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQA
C
D
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
D
E
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
E
F
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
F
G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G
H FT MCH NC VDD VSS VSS VSS VDD NC NC ZZ H
J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
J
K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
K
L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
L
M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
M
N DQB NC VDDQ VSS NC NC NC VSS VDDQ NC NC
N
P
NC NC
A
A TDI A1 TDO A
A
A NC
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04 7/2012
6/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page



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