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GS82582DT21GE の電気的特性と機能

GS82582DT21GEのメーカーはGSI Technologyです、この部品の機能は「288Mb SigmaQuad-II+ Burst of 4 SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS82582DT21GE
部品説明 288Mb SigmaQuad-II+ Burst of 4 SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS82582DT21GE Datasheet, GS82582DT21GE PDF,ピン配置, 機能
165-Bump BGA
Commercial Temp
Industrial Temp
GS82582DT21/39GE-675S/633S/550S
288Mb SigmaQuad-II+
Burst of 4 SRAM
Up to 675 MHz
1.8 V VDD
1.5 V I/O
Features
• For use with GSI FPGA-based Controller IP
• 3.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• 6/6 RoHS-compliant 165-bump BGA package
SigmaQuadFamily Overview
The GS82582DT21/39GE are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582DT21/39GE SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS82582DT21/39GE SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 18 has a
4M addressable index).
tKHKH
Parameter Synopsis
-675S
1.48 ns
-633S
1.58 ns
-550S
1.81 ns
Rev: 1.01 4/2016
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology

1 Page





GS82582DT21GE pdf, ピン配列
GS82582DT21/39GE-675S/633S/550S
16M x 18 SigmaQuad-II+ SRAM—Top View
123456789
A CQ SA SA W BW1 K SA R SA
B NC Q9 D9 SA NC K BW0 SA NC
C NC NC D10 VSS SA NC SA VSS NC
D NC D11 Q10 VSS VSS VSS VSS VSS NC
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Note:
BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
10
SA
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.01 4/2016
3/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology


3Pages


GS82582DT21GE 電子部品, 半導体
GS82582DT21/39GE-675S/633S/550S
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K,K)
input receivers. The input termination is always enabled, and the impedance is programmed via the same RQ resistor (connected
between the ZQ pin and VSS) used to program output driver impedance, in conjunction with the ODT pin (6R). When the ODT pin
is tied Low, input termination is "strong" (i.e., low impedance), and is nominally equal to RQ*0.3 Thevenin-equivalent when RQ is
between 175Ω and 350Ω. When the ODT pin is tied High (or left floating—the pin has a small pull-up resistor), input termination
is "weak" (i.e., high impedance), and is nominally equal to RQ*0.6 Thevenin-equivalent when RQ is between 175Ω and 250Ω.
Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same
manner as for driver impedance (see above).
Note:
Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K inputs should
always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the input
termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to
enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s
operating currents being higher.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20s prior to issuing read and write commands. See the tInit
timing parameter in the AC Electrical Characteristics section.
Note:
The tInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048) must
be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock properly
before issuing read and write commands). However, tInit is greater than tLock, even at the slowest permitted cycle time of 8.4ns
(2048*8.4ns = 17.2s). Consequently, the 20s associated with tInit is sufficient to cover the tLock requirement at power-up if the
Doff pin is driven High prior to the start of the 20s period.
Also, tInit only needs to be met once, immediately after power-up, whereas tLock must be met any time the DLL is disabled / reset
(whether by toggling Doff Low or by stopping K clocks for > 30ns).
Rev: 1.01 4/2016
6/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology

6 Page



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部品番号部品説明メーカ
GS82582DT21GE

288Mb SigmaQuad-II+ Burst of 4 SRAM

GSI Technology
GSI Technology


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