UT04VS33P PDF Data sheet ( 特性 )

部品番号 UT04VS33P
部品説明 Voltage Supervisor
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UT04VS33P Datasheet, UT04VS33P PDF,ピン配置, 機能
Standard Products
UT04VS33P Voltage Supervisor
Data Sheet
July 28, 2014
3.0V to 3.6V Operating voltage range
6 Fixed Threshold Voltage Monitors (3.3V, 2.5V, 1.8V, 1.5V,
1.2V, 1.0V)
Fixed & Adjustable Threshold Voltage Select modes
Threshold Voltage Select with TH0, TH1 pins
Adjustable RESET Timeout with external capacitor
Independent Voltage Monitoring and Sequencing
Manual Reset Input Pin
Active Low and Active High RESET pins
Output Voltages Open Drain
Two VOUTS active high and two VOUTS programmable
with INV Pin
RESET, RESETB Outputs Open Drain
Over-voltage Detection Mode
Operating Temperature Range -55oC to +125oC
Low Power Typical 1000A
Tolerance Select Input Pin (5% & 10%)
guaranteed to be in the correct state for VDD down to 1.2V
Packaging options:
- 28-lead ceramic dual flatpack
Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm2/mg @125oC
- SET Immune: <109MeV-cm2/mg
Standard Microelectronics Drawing (SMD) 5962-13206
- QML Q and V
The UT04VS33P is a radiation-hardened Voltage Supervisor
which simultaneously monitors up to four supply levels utilized
in a system, providing status output for each signal, VOUTx, as
well as, a system reset signal if any of the monitored signals
moves out of range. To set the monitor trip points, the TH0 and
TH1 pins allow the selection of three sets of preset threshold
levels per channel, determined by an internal bandgap voltage
reference, to reduce supply and temperature variance, and a
fourth selection which allows the user to determine the level for
each channel. There are two modes of operation, determined by
the OVSH pin. In the first mode, when the OVSH pin is
connected to VSS, four independent supplies are monitored for
an under-voltage condition. In the second mode when the OVSH
pin is connected to VDD, then under-voltage and over-voltage
of the inputs are monitored. In this mode, two supplies can be
monitored using channels 1 and 3 or channels 2 and 4,
respectively. For flexibility, both system RESET and RESETB
outputs are available for interfacing to the system. Each channel
has an enable, ENx, allowing use of one, two, three or all four
monitor channels.
The margin (or tolerance) to the given threshold voltage, for
under-voltage monitoring, is determined by the setting of the
TOL pin. The logic sense of the channel 3 and 4 outputs can be
inverted by setting the INV pin, appropriately. Also, MRB,
master reset, provides a means for a manual input to activate the
RESET signals. In addition, the user can adjust two timing
parameters by the addition of external capacitors to the device.
These are the response times of the channel VOUTx signal when
the associated input returns to a valid level, implemented by a
capacitor connected to CDLYx and the time to clear RESET (and
RESETB) when a channel enable or input level becomes valid;
implemented by CRESET.
The UT04VS33P supervisory circuit reduces the complexity and
number of circuits required to monitor power supply and battery
functions in microprocessor, DSP, microcontroller, ASIC and
FPGA systems. The UT04VS33P supervisory circuit
significantly improves system reliability and accuracy over
comparable systems that use separate ICs or discrete

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