UT9Q512K32E Datasheet PDF - Aeroflex Circuit Technology
| Part Number | UT9Q512K32E | |
| Description | 16 Megabit RadTolerant SRAM MCM | |
| Manufacturers | Aeroflex Circuit Technology | |
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Standard Products
UT9Q512K32E 16 Megabit RadTolerant SRAM MCM
Data Sheet
June 28, 2011
FEATURES
25ns maximum (5 volt supply) address access time
Asynchronous operation for compatible with industry
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Operational environment:
- Total dose: 50 krads(Si)
- SEL Immune >110 MeV-cm2/mg
- LETTH(0.25) = >52 MeV-cm2/mg
- Saturated Cross Section (cm2) per bit, 2.8E-8
- <1.1E-9 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
(11.0 grams)
Standard Microcircuit Drawing 5962-01511
- QML Q and Vcompliant part
INTRODUCTION
The UT9Q512K32E RadTol product is a high-performance 2M
byte (16Mbit) CMOS static RAM multi-chip module (MCM),
organized as four individual 524,288 x 8 bit SRAMs with a
common output enable. Memory expansion is provided by an
active LOW chip enable (En), an active LOW output enable (G),
and three-state drivers. This device has a power-down feature
that reduces power consumption by more than 90% when
deselected.
Writing to each memory is accomplished by taking chip enable
(En) input LOW and write enable (Wn) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking chip enable (En) and
output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
W3
E3
W2
E2
W1
E1
W0
E0
A(18:0)
G
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
Figure 1. UT9Q512K32E SRAM Block Diagram
DQ(7:0)
or
DQ0(7:0)
1
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DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-40C to +105C (VDD = 5.0V + 10% for (W) screening)
SYMBOL
PARAMETER
CONDITION
VIH
VIL
VOL1
VOL2
VOH1
VOH2
CIN1
CIO1
IIN
IOZ
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
IOS2, 3 Short-circuit output current
IDD(OP)
Supply current operating
@ 1MHz
(per byte)
IDD1(OP)
Supply current operating
@40MHz
(per byte)
IDD2(SB)
Supply current standby
@0MHz
(per byte)
(TTL)
(TTL)
IOL = 8mA, VDD =4.5V (TTL)
IOL = 200A,VDD =4.5V (CMOS)
IOH = -4mA,VDD =4.5V (TTL)
IOH = 200A,VDD =4.5V (CMOS)
= 1MHz @ 0V
= 1MHz @ 0V
VIN = VDD and VSS, VDD = VDD (max)
VO = VDD and VSS
VDD = VDD (max)
G = VDD (max)
VDD = VDD (max), VO = VDD
VDD = VDD (max), VO = 0V
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
Inputs: VIL = VSS
IOUT = 0mA
-40C and
25C
E1 = VDD - 0.5, VDD = VDD (ma1x0)5C
VIH = VDD - 0.5V
Notes:
* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
MIN
2.0
2.4
3.0
-2
-2
-90
MAX
0.8
0.4
0.08
45
UNIT
V
V
V
V
V
V
pF
25 pF
2 A
2 A
90 mA
40 mA
70 mA
9 mA
24 mA
5
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| Information | Total 20 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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