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UT8Q512K32E の電気的特性と機能

UT8Q512K32EのメーカーはAeroflex Circuit Technologyです、この部品の機能は「16 Megabit RadTolerant SRAM MCM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT8Q512K32E
部品説明 16 Megabit RadTolerant SRAM MCM
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT8Q512K32E Datasheet, UT8Q512K32E PDF,ピン配置, 機能
Standard Products
UT8Q512K32E 16 Megabit RadTolerant SRAM MCM
Data Sheet
June 28, 2011
FEATURES
25ns maximum (3.3 volt supply) address access time
MCM contains four (4) 512Kx8 industry-standard
asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24 or 32-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
- SEL Immune >110 MeV-cm2/mg
- SEU LETTH(0.25) = >52 MeV-cm2/mg
- Saturated Cross Section , 2.8E-8 cm2/bit
- <1.1E-9 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
(11.0 grams)
INTRODUCTION
The UT8Q512K32E RadTolerant product is a high-performance
2M byte (16Mbit) CMOS static RAM multi-chip module
(MCM), organized as four individual 524,288 x 8 bit SRAMs
with a common output enable. Memory expansion is provided
by an active LOW chip enable (En), an active LOW output
enable (G), and three-state drivers. This device has a power-
down feature that reduces power consumption by more than 90%
when deselected.
Writing to each memory is accomplished by taking chip enable
(En) input LOW and write enable (Wn) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking chip enable (En) and
output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
Standard Microcircuit Drawing 5962-01533
- QML Q and Vcompliant part
W3
E3
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
W2
E2
W1
E1
W0
E0
A(18:0)
G
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
Figure 1. UT8Q512K32E SRAM Block Diagram
DQ(7:0)
or
DQ0(7:0)
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UT8Q512K32E pdf, ピン配列
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access in Figure 5a,
is defined by a write terminated by Wn going high, with En still
active. The write pulse width is defined by tWLWH when the write
is initiated by Wn, and by tETWH when the write is initiated by
En. Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait tWLQZ before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure 5b,
is defined by a write terminated by the latter of En going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT8Q512K32E SRAM incorporates features which allows
operation in a limited radiation environment.
Table 2. Radiation Hardness
Design Specifications1
Total Dose 50
krad(Si)
Heavy Ion <1.1E-9
Error Rate2
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
3


3Pages


UT8Q512K32E 電子部品, 半導体
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
-40C to +105C (VDD = 3.3V + 0.3V)
SYMBOL
tAVAV1
tAVQV
tAXQX2
tGLQX2
tGLQV
tGHQZ2
tETQX2,3
tETQV3
tEFQZ1,2,4
Read cycle time
PARAMETER
Read access time
Output hold time
G-controlled Output Enable time
G-controlled Output Enable time (Read Cycle 3)
G-controlled output three-state time
En-controlled Output Enable time
En-controlled access time
En-controlled output three-state time
MIN
25
3
3
3
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 500mV change from steady-state output voltage.
3. The ET (chip enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (chip enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
MAX
25
10
10
25
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
High Z to Active Levels
Active to High Z Levels
VLOAD + 300mV
VLOAD
{
{
VLOAD - 300mV
Figure 3. 3.3-Volt SRAM Loading
VH - 300mV
}
}
VL + 300mV
6

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部品番号部品説明メーカ
UT8Q512K32E

16 Megabit RadTolerant SRAM MCM

Aeroflex Circuit Technology
Aeroflex Circuit Technology


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