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PDF UT8Q512E Data sheet ( Hoja de datos )
| Número de pieza | UT8Q512E | |
| Descripción | 512K x 8 RadTol SRAM | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT8Q512E 512K x 8 RadTol SRAM
Data Sheet
November 11, 2008
FEATURES
20ns maximum (3.3 volt supply) address access time
Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Operational environment:
- Total dose: 50 krads(Si)
- SEL Immune 110 MeV-cm2/mg
- SEU LETTH(0.25) = 52 cm2 MeV
- Saturated Cross Section 2.8E-8 cm2/bit
-<1.1E-9 errors/bit-day, Adams 90% worst case
environment geosynchronous orbit
Packaging:
- 36-lead ceramic flatpack (3.831 grams)
Standard Microcircuit Drawing 5962-99607
- QML Q and V compliant part
INTRODUCTION
The UT8Q512E RadTol product is a high-performance CMOS
static RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E), an
active LOW Output Enable (G), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable (E)
and Write Enable (W) inputs LOW. Data on the eight I/O pins
(DQ0 through DQ7) is then written into the location specified
on the address pins (A0 through A18). Reading from the device
is accomplished by taking Chip Enable (E) and Output Enable
(G) LOW while forcing Write Enable (W) HIGH. Under these
conditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected (E HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOW and W LOW).
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ 0 - DQ 7
Memory Array
1024 Rows
512x8 Columns
Data
Control
CLK
Gen.
I/O Circuit
Column Select
E
W
G
Figure 1. UT8Q512E SRAM Block Diagram
1
1 page  
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening (VDD = 3.3V + 0.3V)
SYMBOL
PARAMETER
CONDITION
MIN MAX UNIT
VIH High-level input voltage
(TTL)
2V
VIL
VOL1
Low-level input voltage
Low-level output voltage
(TTL)
IOL = 6mA, VDD = 3.0V (TTL)
0.8 V
0.4 V
VOL2 Low-level output voltage
IOL = 200μA,VDD = 3.0V (CMOS)
0.08 V
VOH1 High-level output voltage
IOH = -3mA,VDD = 3.0V (TTL)
2.4 V
VOH2 High-level output voltage
IOH = -200μA,VDD = 3.0V (CMOS)
VDD-
0.10
V
CIN1 Input capacitance
ƒ = 1MHz @ 0V
10 pF
CIO1
IIN
IOZ
Bidirectional I/O capacitance
ƒ = 1MHz @ 0V
Input leakage current
VIN = VDD and VSS, VDD = VDD (max)
Three-state output leakage current
VO = VDD and VSS
VDD = VDD (max)
G = VDD (max)
12 pF
-2 2 μA
-2 2 μA
IOS2, 3 Short-circuit output current
VDD = VDD (max), VO = VDD
VDD = VDD (max), VO = 0V
-90 90 mA
IDD(OP)4 Supply current operating
@ 1MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
50 mA
IDD(OP)4 Supply current operating
@50MHz
IDD(SB)5 Supply current standby
@0MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
Inputs: VIL = VSS
IOUT = 0mA
E = VDD - 0.5
VDD = VDD (max)
VIH = VDD - 0.5V
76 mA
-55°C,
-40°C, 25°C
125°C
10 mA
45 mA
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. G = V1H
5. Post-radiation limits are the 125oC temperature limits when specified.
5
5 Page 
V DD
DUT
Z o = 5 0 -o h m s
V DD
C L = 40pF
R TERM
1 0 0 -o h m s
R TERM
1 0 0 -o h m s
Test
P o in t
CMOS
VDD-0.05V
10%
0.5V
< 5ns
Input Pulses
90%
10%
< 5ns
Figure 6. AC Test Loads and Input Waveforms
Notes:
1. Measurement of data output occurs at the low to high or high to low
transition mid-point (i.e., CMOS input = VDD/2).
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet UT8Q512E.PDF ] | |
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