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PDF UT54ACS85 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS85 | |
| Descripción | 4-Bit Comparators | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT54ACS85/UT54ACTS85
4-Bit Comparators
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS85 - SMD 5962-96536
UT54ACTS85 - SMD 5962-96537
DESCRIPTION
The UT54ACS85 and the UT54ACTS85 are 4-bit magnitude
comparators that perform comparison of straight binary and
straight BCD (8-4-2-1) codes. Three fully decoded decisions
about two 4-bit words (A, B) are made and are externally avail-
able at three outputs. Devices are fully expandable to any num-
ber of bits without external gates. The cascading paths of the
devices are implemented with only a two-gate-level delay to
reduce overall comparison times for long words. An alternate
method of cascading which further reduces the comparison time
is shown in the typical application data.
The devices are characterized over full military temperature
range of -55°C to +125°C.
LOGIC SYMBOL
A0 (10) 0 COMP
A1 (12)
A2 (13)
A
A3 (15) 3
(A<B)IN (2) <
(A=B)IN (3) =
(A>B)IN (4) >
B0 (9) 0
B1 (11)
B2 (14)
B
< (7) (A<B)OUT
= (6) (A=B)OUT
> (5) (A>B)OUT
B3 (1) 3
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
PINOUTS
16-Pin DIP
Top View
B3
(A<B)IN
(A=B)IN
(A>B)IN
(A>B)OUT
(A=B)OUT
(A<B)OUT
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
A3
B2
A2
A1
B1
A0
B0
B3
(A<B)IN
(A=B)IN
(A>B)IN
(A>B)OUT
(A=B)OUT
(A<B)OUT
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
A3
B2
A2
A1
B1
A0
B0
1
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
6. Maximum allowable relative shift equals 50mV.
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS85.PDF ] | |
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