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UT54ACTS899 の電気的特性と機能

UT54ACTS899のメーカーはAeroflex Circuit Technologyです、この部品の機能は「9-bit Latchable Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54ACTS899
部品説明 9-bit Latchable Transceiver
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT54ACTS899 Datasheet, UT54ACTS899 PDF,ピン配置, 機能
Standard Products
UT54ACTS899
9-bit Latchable Transceiver with Parity Generator/Checker
Datasheet
May 16, 2012
www.aeroflex.com/Logic
FEATURES
Latchable transceiver with output source/sink of 24mA
Option to select generate parity and check or "feed-through"
data/parity in directions A-to-B or B-to-A
Independent latch enable for A-to-B and B-to-A directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
m Commercial CMOS
Operational environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU immune
Standard Microcircuit Drawing 5962-06240
- QML compliant part
Package:
- 28-pin ceramic flatpack
DESCRIPTION
The UT54ACTS899 is a 9-bit to 9-bit parity transceiver with
transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit data
busses in either direction. The UT54ACTS899 features inde-
pendent latch enables for the A-to-B direction and the B-to-A
direction, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
PIN DESCRIPTION
Inputs
A0-A7
B0-B7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Outputs
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for
EVEN Parity
Output Enables for A or B Bus, Active Low
Select Pin for Feed-through or Generate
Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH
for Transparent Mode
Error Signals for Checking Generated Par-
ity with Parity In, LOW if Error Occurs
28-Lead Flatpack
Pinout
ODD/EVEN
ERRA
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
GBA
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
GAB
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
LEB
SEL
ERRB
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UT54ACTS899 pdf, ピン配列
FUNCTIONAL DESCRIPTION
The UT54ACTS899 has three principal modes of operation
which are outlined below. These modes apply to both A-to-B
and B-to-A directions.
- Bus A (B) communicates to Bus B (A), parity is generated
and passed on to the B (A) Bus as BPAR (APAR). If LEB
(LEA) is HIGH and the Mode Select (SEL) is LOW, the parity
generated from B[0:7] (A[0:7]) can be checked and moni-
tored by ERRB (ERRA).
- Bus A (B) communicates to Bus B (A) in a feed-through mode
if SEL is HIGH. Parity is still generated and checked as
ERRA and ERRB in the feed-through mode (can be used as
an interrupt to signal a data/parity bit error to the CPU).
- Independent Latch Enables (LEA and LEB) allow other per-
mutations of generating/checking. (see Function Table below)
FUNCTIONAL TABLE
INPUTS
OPERATION
GAB GBA SEL
HHX
LEA
X
LEB
X Busses A and B are Tri-State (input A & B simultaneously)
H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
H L L H H Generates parity from B[0:7] based on O/E. Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
H L L X L Generates parity from B latch data based on O/E. Generated parity --> APAR.
Generated parity checked against latched BPAR and output as ERRB.
HL
HX
H BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
HL
H H H Generated parity checked against BPAR and output as ERRB.
APAR/A[0:7] fed back through the A latch for generate/check as ERRA.
L H L H L Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
L H L H H Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
L H L L X Generates parity from A latch data based on O/E. Generated parity --> BPAR.
Generated parity checked against latched APAR and output as ERRA.
L H H H L APAR/A[0:7)]--> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
APAR/A[0:7] --> BPAR/B[0:7] Feed-through mode.
L H H H H Generated parity checked against APAR and output as ERRA.
BPAR/B[0:7] fed back through the B latch for generate/check as ERRB.
L L X X X Output to A bus and B bus (NOT ALLOWED).
H = High voltage level
L = Low voltage level
X = Do not care
Note 1: O/E = ODD/EVEN
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UT54ACTS899 電子部品, 半導体
Ptotal Power dissipation7, 8, 9
CL = 20pF
VDD from 4.5 to 5.5
1.0 mW/
MHz
IDDQ Standby Supply Current VDD
Pre-Rad 25oC
Pre-Rad -55oC to +125oC
Post-Rad 25oC
VIN = VDD or VSS
VDD = 5.5
OE=VDD
OE=VDD
OE=VDD
10 A
160 A
IDDQ
Quiescent Supply Current Delta, TTL in-
put level
Pre-Rad 25oC, Pre-Rad -55oC to +125oC
Post-Rad 25oC
For input under test
VIN = VDD - 2.1V
For other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
CIN Input capacitance 10
= 1MHz @ 0V
VDD from 4.5 to 5.5
21 pF
COUT Output capacitance10
= 1MHz @ 0V
VDD from 4.5 to 5.5
21 pF
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested,
for VIN=VIH minimum or VIL maximum.
7. Power dissipation specified per switching output.
8. Guaranteed by characterization.
9. Power does not include power contribution of any CMOS output sink current.
10. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
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部品番号部品説明メーカ
UT54ACTS899

9-bit Latchable Transceiver

Aeroflex Circuit Technology
Aeroflex Circuit Technology


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