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PDF UT54ACS630 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS630 | |
| Descripción | RadHard EDAC | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS630
RadHard EDAC
Datasheet
May 16, 2012
www.aeroflex.com/radhard
FEATURES
DC operating voltage range 4.5V to 5.5V
Input logic levels
- VIL = 30% of VCC
- VIH = 70% of VCC
Fast propagation delay 11ns (max)
m Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU Onset LET: >108 MeV-cm2/mg
Standard Microcircuit Drawing 5962-06239
- QML Q and V
Package:
- 28-lead flatpack
DESCRIPTION
The UT54ACS630 is a RadHard 16-bit parallel error detection
and correction circuit. It uses a modified Hamming code to gen-
erate a 6-bit checkword from each 16-bit data word. The check-
word is stored with the data word during a memory write cycle;
during a memory read cycle a 22-bit word is taken from memory
and checked for errors. Single bit errors in the data words are
flagged and corrected. Single bit errors in the checkword are
flagged, but not corrected. The position of the incorrect bit is
pinpointed, in both cases, by the 6-bit error syndrome code
which is output during the error correction cycle.
PIN DESCRIPTION
Pin Names
Description
S0, S1 Mode Control Inputs
DBn
Bidirectional Data Bus
CBn
Bidirectional Checkbit Bus
SEF
Single Error Flag Output
DEF
Double Error Flag Output
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
VSS
28-Lead Flatpack
Top View
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
SEF
S1
S0
CB0
CB1
CB2
CB3
CB4
CB5
DB15
DB14
DB13
DB12
1
1 page  
CIN Input capacitance6
f= 1MHz @ 0V
VDD from 4.5V to 5.5V
24 pF
COUT Output capacitance6
f= 1MHz @ 0V
VDD from 4.5V to 5.5V
24 pF
VIC+ Positive input clamp voltage
For input under test, IIN = 18mA
VDD = 0.0V
0.4
1.5 V
VIC- Negative input clamp voltage
For input under test, IIN = -18mA
VDD = open
-1.5
-0.4 V
PTOTAL Power dissipation 7, 8, 9
CL = 20pf
VDD from 4.5V to 5.5V
400 W/
MHz
Notes:
1. All specifications valid for radiation dose <1E5 rad(Si) per MIL-STD-883, method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3.Not more than one output may be shorted at a time for maximum duration of one second.
4.Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
7.This value is guaranteed based on characterization data, but not tested.
8.Power does not include power contribution of any CMOS output sink current.
9.Power dissipation specified per switching output.
.
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS630.PDF ] | |
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