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UT54ACS540 の電気的特性と機能

UT54ACS540のメーカーはAeroflex Circuit Technologyです、この部品の機能は「Octal Buffers & Line Drivers」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54ACS540
部品説明 Octal Buffers & Line Drivers
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT54ACS540 Datasheet, UT54ACS540 PDF,ピン配置, 機能
Standard Products
UT54ACS540/UT54ACTS540
Octal Buffers & Line Drivers, Inverted Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Three-state outputs drive bus lines or buffer memory address
registers
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 20-pin DIP
- 20-lead flatpack
‰ UT54ACS540 - SMD 5962-96592
‰ UT54ACTS540 - SMD 5962-96593
DESCRIPTION
The UT54ACS540 and the UT54ACTS540 are inverting octal
buffers and line drivers which improve the performance and
density of three-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OUTPUT
1G 2G An Yn
L L LH
L LHL
HXXZ
XHXZ
LOGIC SYMBOL
1G (1)
2G (19)
&
EN
PINOUTS
1G
A1
A2
A3
A4
A5
A6
A7
A8
VSS
A1 (2)
A2 (3)
A3 (4)
A4 (5)
A5 (6)
A6 (7)
A7 (8)
A8 (9)
(18)
Y1
(17) Y2
(16) Y3
(15) Y4
(14) Y5
(13) Y6
(12) Y7
(11) Y8
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
20-Pin DIP
Top View
1G 1 20 VDD
A1 2 19 2G
A2 3 18 Y1
A3 4 17 Y2
A4 5 16 Y3
A5 6 15 Y4
A6 7 14 Y5
A7 8 13 Y6
A8 9 12 Y7
VSS 10 11 Y8
20-Lead Flatpack
Top View
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
2G
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

1 Page





UT54ACS540 pdf, ピン配列
OPERATIONAL ENVIRONMENT1
PARAMETER
Total Dose
SEU Threshold 2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table
.2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
VI/O
TSTG
TJ
TLS
ΘJC
II
PD
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
-0.3 to 7.0
-.3 to VDD +.3
-65 to +150
+175
+300
20
±10
1
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
VIN
TC
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to VDD
-55 to + 125
UNITS
V
V
°C
3


3Pages


UT54ACS540 電子部品, 半導体
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH An to Yn
tPHL An to Yn
tPZL G low to Yn active
tPZH G low to Yn active
tPLZ G high to Yn three-state
tPHZ G high to Yn three-state
1 12 ns
1 13 ns
2 14 ns
2 15 ns
2 13 ns
2 14 ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
6

6 Page



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Link :


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