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PDF UT54ACS373 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS373 | |
| Descripción | Octal Transparent Latches | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS373/UT54ACTS373
Octal Transparent Latches with Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
8 latches in a single package
Three-state bus-driving true outputs
Full parallel access for loading
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
UT54ACS373 - SMD 5962-96588
UT54ACTS373 - SMD 5962-96589
DESCRIPTION
The UT54ACS373 and the UT54ACTS373 are 8-bit latches
with three-state outputs designed for driving highly capacitive
or relatively low-impedance loads. The device is suitable for
buffer registers, I/O ports, and bidirectional bus drivers.
The eight latches are transparent D latches. While the enable
(C) is high the Q outputs will follow the data (D) inputs. When
the enable is taken low, the Q outputs will be latched at the levels
that were set up at the D inputs.
An output-control input (OC) places the eight outputs in either
a normal logic state (high or low logic levels) or a high-imped-
ance state. The high-impedance third state and increased drive
provide the capability to drive the bus line in a bus-organized
system without need for interface or pull-up components.
The output control OC does not affect the internal operations of
the latches. Old data can be retained or new data can be entered
while the outputs are off.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OUTPUT
OC C nD nQ
L H HH
L H LL
L L X nQ0
H X X Z1
Note:
1. Data may be latched internally.
PINOUTS
20-Pin DIP
Top View
OC 1 20
1Q 2 19
1D 3 18
2D 4 17
2Q 5 16
3Q 6
3D 7
15
14
4D 8 13
4Q 9 12
VSS 10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C
20-Lead Flatpack
Top View
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VSS
LOGIC SYMBOL
(1)
OC
(11)
C
EN
C1
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C
1D (3)
2D (4)
3D (7)
4D (8)
5D (13)
6D (14)
7D (17)
8D (18)
1D
(2)
(5)
1Q
2Q
(6) 3Q
(9) 4Q
(12) 5Q
(15) 6Q
(16) 7Q
(19) 8Q
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS373.PDF ] | |
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