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PDF ISL78223 Data sheet ( Hoja de datos )
| Número de pieza | ISL78223 | |
| Descripción | ZVS Full-Bridge PWM Controller | |
| Fabricantes | Intersil Corporation | |
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ZVS Full-Bridge PWM Controller with AdjustableNOc1NoT-8nOR8ta8ERc-CEItNOCoTOMuErMMRTMSEeINcELhDNonEDricDEwaDFwl OSRwuRE.ipPnNptLeEoArrWsCtiCElD.ceMEonESmteNIG/rTtsNactS
DATASHEET
Synchronous Rectifier Control
ISL78223
The ISL78223 is a high performance zero voltage switching
(ZVS) full-bridge PWM controller. It achieves ZVS operation by
driving the upper bridge FETs at a fixed 50% duty cycle while
the lower bridge FETs are trailing-edge modulated with
adjustable resonant switching delays.
Adding to the ISL78223’s feature set are average current
monitoring and soft-start. The average current signal may be
used for average current limiting, current sharing circuits and
average current mode control. Additionally, the ISL78223
supports both voltage and current mode control.
The ISL78223 features complemented PWM outputs for
synchronous rectifier (SR) control. The complemented outputs
may be dynamically advanced or delayed relative to the PWM
outputs using an external control voltage.
This advanced BiCMOS design features precision deadtime
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, Multi-Pulse
Suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
The ISL78223 is rated for the automotive temperature range
(-40°C to +105°C).
Features
• Adjustable resonant delay for ZVS operation
• Synchronous rectifier control outputs with adjustable
delay/advance
• Voltage or current mode control
• 3% current limit threshold
• Adjustable average current limit
• Adjustable deadtime control
• 175µA start-up current
• Supply UVLO
• Adjustable oscillator frequency up to 2MHz
• Internal over-temperature protection
• Buffered oscillator sawtooth output
• Fast current sense to output delay
• Adjustable cycle-by-cycle peak current limit
• 70ns leading edge blanking
• Multi-pulse suppression
• Pb-free (RoHS compliant)
Applications
• ZVS full-bridge converters
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
FIGURE 1. BOARD LAYOUT
10.0
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0
VIN = 250V
VIN = 350V
VIN = 450V
VO = 13.1V
20 40 60 80 100
LOAD (0-125A) (%)
FIGURE 2. EFFICIENCY vs LOAD
November 20, 2014
FN7936.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Pin Configuration
Pin Descriptions
PIN #
1
PIN NAME
VREF
2 VERR
3 CTBUF
4 RTD
5 RESDEL
6 CT
7 FB
8 RAMP
9 CS
ISL78223
ISL78223
(20 LD QSOP)
TOP VIEW
VREF 1
VERR 2
CTBUF 3
RTD 4
RESDEL 5
CT 6
FB 7
RAMP 8
CS 9
IOUT 10
20 SS
19 VADJ
18 VDD
17 OUTLL
16 OUTLR
15 OUTUL
14 OUTUR
13 OUTLLN
12 OUTLRN
11 GND
DESCRIPTION
The 5V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 2.2µF low ESR capacitor.
The control voltage input to the inverting input of the PWM comparator. The output of an external error
amplifier (EA) is applied to this input, either directly or through an optocoupler, for closed loop regulation.
VERR has a nominal 1mA pull-up current source.
When VERR is driven by an optocoupler or other current source device, a pull-up resistor from VREF is
required to linearize the gain. Generally, a pull-up resistor on the order of 5kΩ is acceptable.
CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing
2mA. It is offset from ground by 0.40V and has a nominal valley-to-peak gain of 2. It may be used for slope
compensation.
This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor
connected between this pin and GND determines the magnitude of the current that discharges CT. The
CT discharge current is nominally 20x the resistor current. The PWM deadtime is determined by the
timing capacitor discharge duration. The voltage at RTD is nominally 2.00V.
Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower
FETs. The voltage applied to RESDEL determines when the upper FETs switch relative to a lower FET
turning on. Varying the control voltage from 0 to 2V increases the resonant delay duration from 0 to 100%
of the deadtime. The control voltage divided by 2 represents the percent of the deadtime equal to the
resonant delay. In practice the maximum resonant delay must be set lower than 2V to ensure that the
lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs.
The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal
200A current source and discharged with a user adjustable current source controlled by RTD.
FB is the inverting inputs to the error amplifier (EA). The amplifier may be used as the error amplifier for
voltage feedback or used as the average current limit amplifier (IEA). If the amplifier is not used, FB
should be grounded.
This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at
the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For
current-mode control this pin is connected to CS and the current loop feedback signal is applied to both
inputs. For voltage mode control, the oscillator sawtooth waveform may be buffered and used to generate
an appropriate signal, RAMP may be connected to the input voltage through a RC network for voltage
feed- forward control, or RAMP may be connected to VREF through a RC network to produce the desired
sawtooth waveform.
This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1V
nominal. The CS pin is shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series input resistor may be required due to the
delay between the internal clock and the external power switch. This delay may result in CS being
discharged prior to the power switching device being turned off.
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5
FN7936.3
November 20, 2014
5 Page 
ISL78223
Functional Description
Features
The ISL78223 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous rectifier
drive. With its many protection and control features, a highly
flexible design with minimal external components is possible.
Among its many features are a very accurate overcurrent limit
threshold, thermal protection, a buffered sawtooth oscillator
output suitable for slope compensation, synchronous rectifier
outputs with variable delay/advance timing, and adjustable
frequency.
Oscillator
The ISL78223 has an oscillator with a programmable frequency
range to 2MHz, which can be programmed with a resistor and
capacitor.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge duration is determined by
CT and a fixed 200µA internal current source. The discharge
duration is determined by RTD and CT.
tC 11.5 103 CT
S
(EQ. 1)
tD 0.06 RTD CT + 50 10–9
tSW = TC + TD = F----S-1---W----
S
S
(EQ. 2)
(EQ. 3)
where tC and tD are the charge and discharge times, respectively,
CT is the timing capacitor in Farads, RTD is the discharge
programming resistance in ohms, tSW is the oscillator period,
and FSW is the oscillator frequency. One output switching cycle
requires two oscillator cycles. The actual times will be slightly
longer than calculated due to internal propagation delays of
approximately 10ns/transition. This delay adds directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very small discharge currents are used, there will
be increased error due to the input impedance at the CT pin. The
maximum recommended current through RTD is 1mA, which
produces a CT discharge current of 20mA.
The maximum duty cycle, D, and percent deadtime, DT, can be
calculated from:
D = t--TS----CW----
(EQ. 4)
DT = 1 – D
(EQ. 5)
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle peak
overcurrent protection which provides fast response. The
cycle-by-cycle peak current limit results in pulse-by-pulse duty cycle
reduction when the current feedback signal exceeds 1.0V. When
the peak current exceeds the threshold, the active output pulse is
immediately terminated. This results in a decrease in output
voltage as the load current increases beyond the current limit
threshold. The ISL78223 operates continuously in an overcurrent
condition without shutdown.
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If voltage
mode control is used, the average overcurrent protection also
maintains flux balance in the transformer by maintaining duty
cycle symmetry between half-cycles. If voltage mode control is
used in a bridge topology, it should be noted that peak current
limit results in inherently unstable operation. The DC blocking
capacitors used in voltage mode bridge topologies become
unbalanced, as does the flux in the transformer core. Average
current limit will prevent the instability and allow continuous
operation in current limit provided the control loop is designed
with adequate bandwidth.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased by
the leading edge blanking (LEB) interval. The effective delay is
the sum of the two delays and is nominally 105ns.
The current sense signal applied to the CS pin connects to the
peak current comparator and a sample and hold averaging
circuit. After a 70ns leading edge blanking (LEB) delay, the
current sense signal is actively sampled during the on time, the
average current for the cycle is determined, and the result is
amplified by 4x and output on the IOUT pin. If an RC filter is
placed on the CS input, its time constant should not exceed
~50ns or significant error may be introduced on IOUT.
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
FIGURE 7. CS INPUT vs IOUT
Figure 7 shows the relationship between the CS signal and IOUT
under steady state conditions. The IOUT is 4x the average of CS.
Figure 8 shows the dynamic behavior of the current averaging
circuitry when CS is modulated by an external sine wave. Notice
IOUT is updated by the sample and hold circuitry at the
termination of the active output pulse.
Submit Document Feedback 11
FN7936.3
November 20, 2014
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL78223.PDF ] | |
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