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PDF ISL70003ASEH Data sheet ( Hoja de datos )
| Número de pieza | ISL70003ASEH | |
| Descripción | 9A Buck Regulator | |
| Fabricantes | Intersil | |
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DATASHEET
Radiation and SEE Tolerant 3V to 13.2V, 9A Buck
Regulator
ISL70003ASEH
The ISL70003ASEH is an improved version of the ISL70003SEH
regulator with both tighter load regulation (<0.3% typical) and a
higher output current rating of 9A. Operating over an input voltage
range of 3.0V to 13.2V, with integrated low rDS(ON) MOSFETs
makes this monolithic solution highly efficient. Also, a tightly
regulated output voltage is possible, which is externally
adjustable from 0.6V to ~90% of the input voltage. Continuous
output load current capability is 9A for TJ ≤+125°C and 6A for
TJ ≤+150°C.
The ISL70003ASEH uses voltage mode control architecture
with feed-forward and switches at a selectable frequency of
500kHz or 300kHz. Loop compensation is externally
adjustable to allow for an optimum balance between stability
and output dynamic performance.
The device features two logic-level disable inputs that can be
used to inhibit pulses on the phase (LXx) pins in order to
maximize efficiency based on the load current. The
ISL70003ASEH also supports DDR applications and contains a
buffer amplifier for generating the VREF voltage.
High integration, best in class radiation performance and a
feature filled design make the ISL70003ASEH an ideal choice
to power many of todays small form factor applications.
All existing ISL70003SEH supporting collateral is relevant to
the ISL70003ASEH and can be used as such.
Applications
• FPGA, CPLD, DSP, CPU core and I/O supply voltages
• DDR memory supply voltages
• Low-voltage, high-density distributed power systems
Related Literature
• AN1897, “ISL70003SEHEV1Z Evaluation Board”
• AN1915, “ISL70003SEH iSim:PE Model”
• TR009, “Single Event Effects (SEE) Testing of the
ISL70003ASEH POL BUCK Regulator”
• AN1924, “Total Dose Testing of the ISL70003SEH Radiation
Hardened Point Of Load Regulator”
• TB502, “High Power ISL70003ASEH High Temperature
Operating Life (HTOL) and Overcurrent Abuse“
• UG046, “ISL70003ASEHEV2Z Evaluation Board User Guide”
Features
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
• ±1% reference voltage over line, temperature and radiation
• Integrated MOSFETs 31mΩPFET/21mΩ NFET
- 95% peak efficiency
• Externally adjustable loop compensation
• Supports DDR applications (VTT tracks VDDQ/2)
- Buffer amplifier for generating VREF voltage
- 3A current sinking capability
• Grounded lid eliminates charge build up
• IMON pin for output current monitoring
• Adjustable analog soft-start
• Diode emulation for increased efficiency at light loads
• 500kHz or 300kHz operating frequency
• Monotonic start-up into prebiased load
• Full military temperature range operation
- TA = -55°C to +125°C
- TJ = -55°C to +150°C
• Radiation tolerance
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Limit established by characterization.
• SEE hardness
- SEB and SEL LETTH . . . . . . . . . . . . . . . . 86.4MeV•cm2/mg
- SET at LET 86.4MeV•cm2/mg . . . . . . . . . . . < ±3% ΔVOUT
- SEFI LETTH . . . . . . . . . . . . . . . . . . . . . . . . . 60MeV•cm2/mg
• Electrically screened to DLA SMD 5962-14203
0.3
0.2
-55°C
0.1
+25°C
+125°C
0.0
-0.1
+85°C
-0.2
-0.3
0123456789
LOAD CURRENT (A)
FIGURE 1. TYPICAL LOAD REGULATION, VIN = 12V, VOUT = 3.3V,
fSW = 500kHz
May 12, 2016
FN8746.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Pin Configuration
BOTTOM SIDE DETAIL
FOR PIN 1 LOCATION
ISL70003ASEH
ISL70003ASEH
(64 LD CQFP)
TOP VIEW
1 (NI) NI
FB
VERR
POR_VIN
VREFA
AVDD
AGND
DGND
VREF_OUTS
DVDD
VREFD
ENABLE
RT/CT
FSEL
SYNC
SS_CAP
1 64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
2 47
3 46
4 45
5 44
6 (Note 3)
43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14
HEATSINK OUTLINE *
35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LX3
PGND3
PGND4
LX4
PVIN4
PVIN5
LX5
PGND5
PGND6
LX6
PVIN6
PVIN7
LX7
PGND7
PGND8
LX8
NOTE:
3. The ESD triangular mark is indicative of pin #1 location. It is part of the device marking and is
placed on the lid in the quadrant where pin #1 is located.
* Indicates heatsink package R64.C
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
PIN NAME
NI
FB
VERR
POR_VIN
VREFA
AVDD
ESD CIRCUIT
DESCRIPTION
1 This pin is the noninverting input to the internal error amplifier. Connect this pin to the REF pin for
typical applications or the BUFOUT pin for DDR memory power applications.
1 This pin is the inverting input to the internal error amplifier. An external type III compensation network
should be connected between this pin and the VERR pin. The connection between the FB resistor divider
and the output inductor should be a Kelvin connection to optimize performance.
1 This pin is the output of the internal error amplifier. An external compensation network should be
connected between this pin and the FB pin.
1 This pin is the power-on reset input to the IC. This is a comparator-type input with a rising threshold of
0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
3 This pin is the output of the internal linear regulator and the bias supply input to the internal analog
control circuitry. Locally filter this pin to AGND using a 0.47µF ceramic capacitor as close as possible to
the IC.
5 This pin provides the supply for the internal linear regulator of the ISL70003ASEH. The supply to AVDD
should be locally bypassed using a ceramic capacitor. Tie AVDD to the PVINx pins.
Submit Document Feedback
5
FN8746.1
May 12, 2016
5 Page 
ISL70003ASEH
Electrical Specifications Unless otherwise noted, PVINx = AVDD = DVDD = 3V - 13.2V; GND = AGND = DGND = PGNDx = SGND = 0V;
POR_VIN = 0.65V; SYNC = LXx = Open Circuit; PGOOD is pulled up to VREFD with a 3k resistor; REF is bypassed to GND with a 220nF capacitor; SS is
bypassed to GND with a 100nF capacitor; IOUT = 0A; TA = TJ = +25°C. (Note 4). Boldface limits apply across the operating temperature range, -55°C to
+125°C; over a total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s; or over a total ionizing dose of 50krad(Si) with
exposure at a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
POWER-ON RESET
POR Pin Input Voltage
0.56
0.6
0.64
V
POR Sink Current
9.6 12 14.4
µA
ENABLE
Enable VIH Voltage
2V
Enable VIL Voltage
0.8 V
Enable (EN) Leakage
EN = 4.5V
1.0 10
µA
SELECT PHASE
SEL 1, 2 VIH Voltage
2V
SEL 1, 2 VIL Voltage
0.8 V
SEL 1, 2 Leakage Current
SEL1, 2 = VREFD
1.0 10
µA
PWM CONTROL LOGIC
Switching Frequency
FSEL = 1
255 300
345
kHz
FSEL = 0
425 500
575
kHz
Minimum On Time
SS = GND (Note 12)
250 320
ns
Minimum On Time
(Note 12)
160 220
ns
Minimum Off Time
(Note 12)
200 270
ns
Modulator Gain (VIN /ΔVOSC)
RT = 22kΩ, CT = 370pF, FSEL = 0
RT = 36kΩ, CT = 370pF, FSEL = 1
External Synchronization Frequency Range FSEL = 1, PVINx = 3.0V
FSEL = 0, PVINx = 3.0V
SYNC VIH Voltage
5
4.8
255 300
425 500
2
345
575
V/V
V/V
kHz
kHz
V
SYNC VIL Voltage
0.8 V
Synchronization Input Leakage Current SYNC = VREFD
1.0 4
µA
SOFT-START
Soft-start Source Current
SS = GND
20 23
27
µA
Soft-start Discharge ON-Resistance
3.0 6.0
Ω
Soft-start Discharge Time
(Note 12)
256 Clock Cycles
REFERENCE VOLTAGE
Reference Voltage Tolerance
LOAD REGULATION
VREF including Error Amplifier VIO
0.594
0.6
0.606
V
Output Voltage Tolerance over Output
Current Range
PVIN = 3V - 13.2V, to 9A
(Notes 11, 12)
-0.45
-0.05
0.25
%
Submit Document Feedback 11
FN8746.1
May 12, 2016
11 Page | ||
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| PDF Descargar | [ Datasheet ISL70003ASEH.PDF ] | |
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