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PDF ISL68201 Data sheet ( Hoja de datos )
| Número de pieza | ISL68201 | |
| Descripción | Single-Phase R4 Digital Hybrid PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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DATASHEET
SPiMnBglues-P/ShMasBeuRs/4I™2CDaignidtaPlFHMybrid PWM Controller with
ISL68201
The ISL68201 is a single-phase, synchronous buck PWM
controller featuring Intersil’s proprietary R4™ Technology. It
supports a wide 4.5V to 24V input voltage range and a wide
0.5V to 5.5V output range. Integrated LDOs provide controller
bias voltage, allowing for single supply operation. The
ISL68201 includes a PMBus/SMBus/I2C interface for device
configuration and telemetry (VIN, VOUT, IOUT and temperature)
and fault reporting.
Intersil’s proprietary R4™ control scheme has extremely fast
transient performance, accurately regulated frequency control
and all internal compensation. An efficiency enhancing PFM
mode can be enabled to greatly improve light-load efficiency.
The ISL68201’s series bus allows for easy R4™ loop
optimization, resulting in fast transient performance over a
wide range of applications, including all ceramic output filters.
The ISL68201 has four 8-bit configuration pins, which provide
very flexible configuration options (frequency, VOUT, R4™ gain,
etc.) without the need for built-in NVM memory. This results in
a design flow that closely matches traditional analog
controllers, while still offering the design flexibility and feature
set of a digital PMBus/SMBus/I2C interface. The ISL68201
also features remote voltage sensing and completely eliminates
any potential difference between remote and local grounds. This
improves regulation and protection accuracy. A precision enable
input is available to coordinate the start-up of the ISL68201 with
other voltage rails, especially useful for power sequencing.
Applications
• High efficiency and high density POL digital power
• FPGA, ASIC and memory supplies
• Data center: servers, storage systems
• Wired infrastructure: routers/switches/optical networking
• Wireless infrastructure: base station
Related Literature
• UG068, “ISL68201-99140DEMO1Z User Guide”
Features
• Intersil’s proprietary R4™ Technology
- Linear control loop for optimal transient response
- Variable frequency and duty cycle control during load
transient for fastest possible response
- Inherent voltage feed-forward for wide range input
• Input voltage range: 4.5V to 24V
• Output voltage range: 0.5V to 5.5V
• ±0.5% DAC accuracy with remote sense
• Support all ceramic solutions
• Integrated LDOs for single input rail solution
• SMBus/PMBus/I2C compatible, up to 1.25MHz
• 256 boot-up voltage levels with a configuration pin
• Eight switching frequency options from 300kHz to 1.5MHz
• PFM operation option, compatible with ISL99140 for
improved light-load efficiency
• Start-up into precharged load
• Precision enable input to set higher input UVLO and power
sequence as well as fault reset
• Power-good monitor for soft-start and fault detection
• Comprehensive fault protection for high system reliability
- Over-temperature protection
- Output overcurrent and short-circuit protection
- Output overvoltage and undervoltage protection
- Open remote sense protection
• Compatible with 5V or 3.3V PWM input DrMOS or Smart
Power Stage (SPS)
• Compatible with Intersil’s PowerNavigator™ software
PART
NUMBER
ISL68200
ISL68201
INTEGRATED
DRIVER
Yes
No
TABLE 1. SINGLE-PHASE R4™ DIGITAL HYBRID PWM CONTROLLER OPTIONS
PWM PMBus/SMBus/I2C
OUTPUT
INTERFACE
COMPATIBLE DEVICES
No Yes Discrete MOSFETs or Dual Channel MOSFETs
Yes Yes Intersil Power Stages:
ISL99140
Intersil Drivers:
ISL6596, ISL6609, ISL6627, ISL6622, ISL6208
March 7, 2016
FN8696.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design), R3 Technology, R4 Technology and PowerNavigator are trademarks owned by Intersil Corporation or
one of its subsidiaries.All other trademarks mentioned are the property of their respective owners.
1 page  
ISL68201
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL68201IRZ
ISL 68201I
-40 to +85
24 Ld 4x4 QFN
L24.4x4C
ISL68201-99140DEMO1Z
35A Demo Board with On-Board Transient
NOTES:
1. Add “-T” suffix for 6k unit, “-T7A” suffix for 250 unit or “-TK” for 1k unit for Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL68201. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL68201
(24 LD 4X4 QFN)
TOP VIEW
24 23 22 21 20 19
EN 1
18 PROG1
VIN 2
17 PROG2
7VLDO 3
VCC 4
GND
(PAD)
16 PROG3
15 PROG4
SCL 5
14 IOUT
SALERT 6
13 NTC
7 8 9 10 11 12
Functional Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
DESCRIPTION
EN Precision enable input. Pulling EN above the rising threshold voltage initiates the soft-start sequence, while pulling EN below the
failing threshold voltage suspends the Voltage Regulator (VR) operation.
VIN Input voltage pin for R4 loop and LDOs (5V and 7V). Place a high quality low ESR ceramic capacitor (1.0μF, X7R) in close
proximity to the pin. External series resistor is not advised.
7VLDO 7V LDO from VIN is used to bias current sensing amplifier. Place a high quality low ESR ceramic capacitor (1.0μF, X7R, 10V+)
in close proximity to the pin.
VCC Logic bias supply that should be connected to PVCC rail externally. Place a high quality low ESR ceramic capacitor (1μF,
X7R) from this pin to GND.
SCL Synchronous clock signal input of SMBus/PMBus/I2C.
SALERT Output pin for transferring the active low signal driven asynchronously from the VR controller to SMBus/PMBus.
SDA I/O pin for transferring data signals between SMBus/PMBus/I2C host and VR controller.
PGOOD Power-good open-drain indicator output.
RGND This pin monitors the negative rail of regulator output. Connect to ground at point of regulation.
VSEN This pin monitors the positive rail of regulator output. Connect to point of regulation.
CSRTN This pin monitors the negative flow of output current for overcurrent protection and telemetry.
Submit Document Feedback
5
FN8696.1
March 7, 2016
5 Page 
ISL68201
Tables 3 to 6 show the RUP and RDW values of each pin for a
specific system design with some tie-high and tie-low options,
which are for easy programming with reduced resistors and can
be used to validate the regulator operation during In-circuit Test
(ICT) for 0V boot-up voltage option. Additional options are
available Intersil’s PowerNavigator™ GUI or Resistor Reader
calculator, please contact Intersil Application support at
www.intersil.com/en/support. DATA for corresponding registers
can be read out via series bus command (DC to DF). Note that
more options are in PowerNavigator™ GUI or Resistor Reader
calculator and the case of 10kΩ tie-high or tie-low is equivalent
0Ω tie-high or tie-low.
TABLE 3. PROG 1 RESISTOR READER EXAMPLE
PROG1 RUP RDW
(DC) (kΩ) (kΩ)
VOUT
(V)
00h Open 0
0.797
20h Open 21.5
0.852
40h Open 34.8
0.898
60h Open 52.3
0.953
80h Open 75
1.000
A0h Open 105
1.047
C0h Open 147
1.102
E0h Open 499
1.203
1Fh 0 Open
1.352
3Fh 20 Open
1.500
5Fh 34.8 Open
1.797
7Fh 52.3 Open
2.500
9Fh 75 Open
3.000
BFh 105 Open
3.297
DFh 147 Open
5.000
FFh 499 Open
0.000
TABLE 4. PROG 2 RESISTOR READER EXAMPLE
PROG2 RUP RDW
TEMP
(DD) (kΩ) (kΩ) PWM/PFM COMP
PM_ADDR
(7-BIT)
00h Open 0
Enabled
30
60h
20h Open 21.5 Enabled
15
60h
40h Open 34.8 Enabled
5
60h
60h Open 52.3 Enabled
OFF
60h
80h Open 75 Disabled
30
60h
A0h Open 105 Disabled
15
60h
C0h Open 147 Disabled
5
60h
E0h Open 499 Disabled
OFF
60h
1Fh 0 Open Enabled
30
7F
3Fh 21.5 Open Enabled
15
7F
5Fh 34.8 Open Enabled
5
7F
TABLE 4. PROG 2 RESISTOR READER EXAMPLE (Continued)
7Fh 52.3 Open Enabled
OFF
7F
9Fh 75 Open Disabled
30
7F
BFh 105 Open Disabled
15
7F
DFh 147 Open Disabled
5
7F
FFh 499 Open Disabled
OFF
7F
TABLE 5. PROG 3 RESISTOR READER EXAMPLE
PROG3 RUP
(DE) (kΩ)
RDW ULTRASONIC FAULT
fSW
(kΩ) PFM BEHAVIOR (kHz)
R4 GAIN
1x 2x
00h Open 0
Disabled
Retry
300 42 84
20h Open 21.5 Disabled
Retry
700 42 84
40h Open 34.8 Disabled
Latch
300 42 84
60h Open 52.3 Disabled
Latch
700 42 84
80h Open 75 Enabled
Retry
300 42 84
A0h Open 105 Enabled
Retry
700 42 84
C0h Open 147 Enabled
Latch 300 42 84
E0h Open 499 Enabled
Latch 700 42 84
1Fh 0 Open Disabled Retry 600 1 2
3Fh 21.5 Open Disabled
Retry 1500 1 2
5Fh 34.8 Open Disabled
Latch
600 1 2
7Fh 52.3 Open Disabled
Latch 1500 1 2
9Fh 75 Open Enabled
Retry
600 1 2
BFh 105 Open Enabled
Retry 1500 1 2
DFh 147 Open Enabled
Latch 600 1 2
FFh 499 Open Enabled
Latch 1500 1 2
TABLE 6. PROG 4 RESISTOR READER EXAMPLE
PROG4 RUP RDW
(DF (kΩ) (kΩ)
SS RATE
(mV/µs)
RR
(k
00h Open 0
1.25
200
20h Open 21.5
2.5
200
40h Open 34.8
5
200
60h Open 52.3
10
200
80h Open 75
0.078
200
A0h Open 105
0.157
200
C0h Open 147
0.315
200
E0h Open 499
0.625
200
1Fh
0 Open
1.25
800
3Fh 21.5 Open
2.5
800
5Fh 34.8 Open
5
800
7Fh 52.3 Open
10
800
AVMLTI
1x
1x
1x
1x
1x
1x
1x
1x
2x
2x
2x
2x
Submit Document Feedback 11
FN8696.1
March 7, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL68201.PDF ] | |
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