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PDF STA369BW Data sheet ( Hoja de datos )
| Número de pieza | STA369BW | |
| Descripción | 2.1-channel high-efficiency digital audio system | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STA369BW
2.1-channel high-efficiency digital audio system
Sound Terminal®
Datasheet - production data
PowerSSO-36
with exposed pad down (EPD)
Features
Wide-range supply voltage
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
Four power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 30 W into 8 at 22 V)
– 3 channels - left, right using binary and LFE
using ternary PWM (2.1 mode) (2 x 15 W +
1 x 30 W into 2 x 4, 1 x 8 at 22 V)
– 2 channels of ternary PWM (2 x 30 W) +
stereo lineout ternary)
FFX®100 dB SNR and dynamic range
Selectable 32 to 192 kHz input sampling rates
I2C control with selectable device address
Digital gain/attenuation +42 dB to -80 dB with
0.125 dB/step resolution
Soft-volume update with programmable ratio
Individual channel and master gain/attenuation
Two independent DRCs configurable as a
dual-band anti-clipper (B2DRC) or independent
limiters/compressors
EQ-DRC for DRC based on filtered signals
Dedicated LFE processing for bass boosting
with 0.125 dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset nighttime listening mode
Individual channel and master soft/hard mute
Independent channel volume and DSP bypass
Automatic zero-detect mute
Automatic invalid input-detect mute
I2S input data interface
Input and output channel mapping
Up to 8 user-programmable biquads per
channel
3 coefficient banks for EQ presets storing with
fast recall via I2C interface
Extended coefficient dynamic up to -4..4 for
easy implementation of high shelf filters
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high- or low-bandwidth
noise-shaping topologies
Selectable clock input ratio
96 kHz internal processing sampling rate with
quantization error noise shaping for very low
cutoff frequency filters
Thermal overload and short-circuit protection
embedded
Video apps: 576 x Fs input mode supported
Fully compatible with STA339BW,
STA369BWS and STA350BW
Table 1. Device summary
Order code
Package
Packing
STA369BW Power SSO-36
Tube
STA369BWTR Power SSO-36 Tape and reel
September 2013
This is information on a product in full production.
DocID022033 Rev 2
1/89
www.st.com
1 page  
STA369BW
Contents
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.11.5 Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 62
8.11.6 Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 62
8.11.7 Limiter 2 extended attack threshold (addr 0x34) . . . . . . . . . . . . . . . . . . 63
8.11.8 Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 63
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 63
8.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.12.21 Overcurrent post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 70
Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 70
Fault-detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 71
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 72
Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 73
DocID022033 Rev 2
5/89
89
5 Page 
STA369BW
1.1 Block diagram
Figure 1. Block diagram
2
IS
in terfa ce
I2C
Pro tection
curre nt/the rm al
C han nel
1A
Description
Vo lu me
c ontr ol
FFX
Pow er
co ntro l
PLL
D ig ita l DSP
Log ic
C hann el
1B
R egulat ors
Bias
Ch anne l
2A
C hann el
2B
Po w er
AM045167v1
DocID022033 Rev 2
11/89
89
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STA369BW.PDF ] | |
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