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PDF CG7501AA Data sheet ( Hoja de datos )
| Número de pieza | CG7501AA | |
| Descripción | 4-Mbit (512 K x 8) nvSRAM | |
| Fabricantes | Cypress | |
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CG7501AA
4-Mbit (512 K × 8) nvSRAM
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
■ 45 ns access time
■ Internally organized as 512 K × 8
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20, –10 operation
■ Industrial temperature
■ Package
❐ 48-ball fine-pitch ball grid array (FBGA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CG7501AA is a fast static RAM (SRAM), with a
non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each. The embedded
non-volatile elements incorporate QuantumTrap technology,
producing the world’s most reliable non-volatile memory. The
SRAM provides infinite read and write cycles, while independent
non-volatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the non-volatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the non-volatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A 17
A 18
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
QuantumTrap
2048 X 2048
STORE
STATIC RAM
ARRAY
2048 X 2048
RECALL
COLUMN I/O
COLUMN DEC
A9 A10 A11A12 A13A14A15 A16
VCC VCAP
POWER
CONTROL
STORE/RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A14 A2
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-82292 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 5, 2012
1 page  
CG7501AA
Device Operation
The CG7501AA nvSRAM is made up of two functional
components paired in the same physical cell. They are a SRAM
memory cell and a non-volatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CG7501AA supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the non-volatile cells and up to 1 million STORE operations.
Refer to the Truth Table For SRAM Operations on page 16 for a
complete description of read and write modes.
SRAM Read
The CG7501AA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0–18 determines which of the 524,288 data bytes are accessed.
When the read is initiated by an address transition, the outputs
are valid after a delay of tAA (read cycle 1). If the read is initiated
by CE or OE, the outputs are valid at tACE or at tDOE, whichever
is later (read cycle 2). The data output repeatedly responds to
address changes within the tAA access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid (tSD time) before the
end of a WE controlled write or before the end of an CE
controlled write. It is recommended that OE be kept HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore Operation
The CG7501AA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by the HSB; Software STORE activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CG7501AA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 7. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
VCC
0.1 uF
VCC
WE VCAP
VSS
VCAP
Hardware STORE Operation
The CG7501AA provides the HSB pin to control and
acknowledge the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CG7501AA conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a write to the
SRAM has taken place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CG7501AA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other external
source.
During any STORE operation, regardless of how it is initiated,
the CG7501AA continues to drive the HSB pin LOW, releasing it
Document Number: 001-82292 Rev. **
Page 5 of 20
5 Page 
CG7501AA
AC Switching Characteristics
Over the Operating Range
Parameters [11]
Cypress
Parameter
Alt Parameter
SRAM Read Cycle
tACE
tRC[12]
tAA[13]
tACS
tRC
tAA
tDOE
tOHA[13]
tLZCE[14, 15]
tHZCE[14, 15]
tLZOE[14, 15]
tHZOE[14, 15]
tPU[14]
tPD[14]
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE[14, 15, 16]
tLZWE[14, 15]
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
45 ns
Min Max
Unit
– 45 ns
45 – ns
– 45 ns
– 20 ns
3 – ns
3 – ns
– 15 ns
0 – ns
– 15 ns
0 – ns
– 45 ns
45 – ns
30 – ns
30 – ns
15 – ns
0 – ns
30 – ns
0 – ns
0 – ns
– 15 ns
3 – ns
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [12, 13, 17]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
tOHA
Output Data Valid
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 3 on page 10.
12. WE must be HIGH during SRAM read cycles.
13. Device is continuously selected with CE and OE LOW.
14. These parameters are guaranteed by design but not tested.
15. Measured ±200 mV from steady state output voltage.
16. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
17. HSB must remain HIGH during read and write cycles.
Document Number: 001-82292 Rev. **
Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CG7501AA.PDF ] | |
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