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H9TQ17ABJTMCUR-KTM の電気的特性と機能

H9TQ17ABJTMCUR-KTMのメーカーはHynix Semiconductorです、この部品の機能は「16GB eNAND (x8) / LPDDR3 16Gb(x32)」です。


製品の詳細 ( Datasheet PDF )

部品番号 H9TQ17ABJTMCUR-KTM
部品説明 16GB eNAND (x8) / LPDDR3 16Gb(x32)
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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H9TQ17ABJTMCUR-KTM Datasheet, H9TQ17ABJTMCUR-KTM PDF,ピン配置, 機能
CI-MCP Specification
16GB eNAND (x8)
+ 16Gb LPDDR3 (x32)
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 0.1 / Mar. 2014
1

1 Page





H9TQ17ABJTMCUR-KTM pdf, ピン配列
Preliminary
H9TQ17ABJTMCUR series
16GB eNAND (x8) / LPDDR3 16Gb(x32)
FEATURES
[ CI-MCP ]
Operation Temperature
- (-25)oC ~ 85oC
Package
- 221-ball FBGA - 11.5x13.0mm2, 1.0t, 0.5mm pitch
- Lead & Halogen Free
[ e-NAND ]
[ LPDDR3 ]
eMMC5.0 compatible
(Backward compatible to eMMC4.5)
Bus mode
- Data bus width : 1 bit(default), 4 bits, 8 bits
- Data transfer rate: up to 400MB/s (HS400)
- MMC I/F Clock frequency : 0~200MHz
- MMC I/F Boot frequency : 0~52MHz
Operating voltage range
- Vcc (NAND) : 2.7 - 3.6V
- Vccq (Controller) : 1.7 - 1.95V / 2.7 - 3.6V
Temperature
- Operation (-25~ +85)
- Storage without operation (-40~ +85)
Others
- This product is compliance with the RoHS
directive
   Supported features
- HS400, HS200
- HPI, BKOPS
- Packed CMD, Cache
- Partitioning, RPMB
- Discard, Trim, Erase, Sanitize
- Write protect, Lock / Unlock
- PON, Sleep / Awake
- Reliable write
- Boot feature, Boot partition
- HW / SW Reset
- Field firmware update
- Configurable driver strength
- Health(Smart) report
- Production state awareness
- Secure removal type
VDD1 = 1.8V (1.7V to 1.95V)
VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
HSUL_12 interface (High Speed Unterminated Logic 1.2V)
Double data rate architecture for command, address and
data Bus;
- all control and address except CS_n, CKE latched at both
rising and falling edge of the clock
- CS_n, CKE latched at rising edge of the clock
- two data accesses per clock cycle
Differential clock inputs (CK_t, CK_c)
Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-direc-
tional differential data strobe (DQS_t, DQS_c)
- Data outputs aligned to the edge of the data strobe
(DQS_t, DQS_c) when READ operation
- Data inputs aligned to the center of the data strobe
(DQS_t, DQS_c) when WRITE operation
DM masks write data at the both rising and falling edge of
the data strobe
Programmable RL (Read Latency) and WL (Write Latency)
Programmable burst length: 8
Auto refresh and self refresh supported
All bank auto refresh and per bank auto refresh supported
Auto TCSR (Temperature Compensated Self Refresh)
PASR (Partial Array Self Refresh) by Bank Mask and Segment
Mask
DS (Drive Strength)
DPD (Deep Power Down)
ZQ (Calibration)
ODT (On Die Termination)
Rev 0.1 / Mar. 2014
3


3Pages


H9TQ17ABJTMCUR-KTM 電子部品, 半導体
Ball ASSIGNMENT
Preliminary
H9TQ17ABJTMCUR series
16GB eNAND (x8) / LPDDR3 16Gb(x32)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A DNU VSF VSSm VCCQ DAT6 CMD DS VSSm DAT0 DAT5 VDDI VSSm VSF DNU A
B VSF VSSm VCC DAT7 DAT3 VCCQ VSSm CLKm VCCQ DAT1 VSSm VCC VCC VSF B
C
RST VSSm VCC VSSm DAT2 VCCQ VSSm DAT4 VSSm VCCQ VSSm VSSm
C LPDDR3
D VSF VSF VSF VSF VSF VSSm VCC
Commend/Address
D LPDDR3 Data IO
E
F VSS VDD1 VDD1 VDD2
VDD2 VDD1 DQ29 DQ30 DQ31 VSS
E
eMMC
F IO/Commend
G ZQ NC VSS VDD1
H CA9 VSS VSS VSS
J CA8 CA7 VSS VDD2
K VDDCA CA6 VSS VDD2
L VDD2 CA5 VSS VDD2
M VREFCA VSS VSS VDD2
N
VDDCA
CLK_
c
VSS
VDD2
P VSS CLK_t VSS VDD2
R CKE1 VSS VSS VDD2
T
CKE0
CS1_
n
VSS
VDD2
U
VDDCA
CS0_
n
VSS
VDD2
V VDDCA CA4 VSS VDD2
W CA2 CA3 VSS VDD2
Y CA0 CA1 VSS VSS
AA DNU VSS VDD1 VSS VDD1
VSS VDDQ DQ26 VSS DQ27 DQ28
VDDQ
DQS3
_t
VSS
DQ24 VDDQ DQ25
VSS
DQS3
_c
DM3
VDDQ DQ15
VSS
VSS VSS VDDQ DQ13 VDDQ DQ14
VDDQ VDDQ VSS DQ12 VSS DQ11
VSS
DQS1
_t
VDDQ
DQ10
VDDQ
DQ9
VSS
DQS1
_c
DM1
VDDQ
DQ8
VSS
VDD2 VSS ODT VDD2 VSS VREFDQ
VSS
DQS0
_c
DM0
VDDQ
DQ7
VSS
VSS
DQS0
_t
VDDQ
DQ5
VDDQ DQ6
VDDQ VDDQ VSS DQ3 VSS DQ4
VSS VSS VDDQ DQ1 VDDQ DQ2
VSS
DQS2
_c
DM2
VDDQ
DQ0
VSS
VDDQ
DQS2
_t
VSS
DQ23 VDDQ DQ22
VSS VDDQ DQ21 VSS DQ20 DQ19 DNU
G
H Power
(VDD1,VDD2,
J VDDCA,VREF)
Ground
K (VSS,VSSCA,VSSQ)
L
M
N
P
R
T
U
V
W
Y
AA
AB DNU DNU VDD1 VDD1 VDD2
VDD2 VDD1 DQ18 DQ17 DQ16 DNU DNU
AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Top View
221ball MCP
eMMC + x32 LPDDR3 (1CH)
Note: 1. Vendor specific function (VSF) - this terminal should not have any external electrical connections, but it may have an internal
connection. The terminal may be routed to provide accessability and may be used for general purpose vendor specific operations.
Rev 0.1 / Mar. 2014
6

6 Page



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部品番号部品説明メーカ
H9TQ17ABJTMCUR-KTM

16GB eNAND (x8) / LPDDR3 16Gb(x32)

Hynix Semiconductor
Hynix Semiconductor


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