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PDF CR8F6125 Data sheet ( Hoja de datos )
| Número de pieza | CR8F6125 | |
| Descripción | 16 MHz CR8F 8-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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CR8F612X
16 MHz CR8F 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM,
640 bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C
Preliminary data
Features
Core
■ 16 MHz advanced CR8Fcore with Harvard
architecture and 3-stage pipeline
■ Extended instruction set
Memories
■ Program memory: 8 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles
■ Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
■ RAM: 1 Kbytes
Clock, reset and supply management
■ 2.95 to 5.5 V operating voltage
■ Flexible clock control, 4 master clock sources:
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
■ Clock security system with clock monitor
■ Power management:
– Low power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
■ Permanently active, low consumption power-
on and power-down reset
Interrupt management
■ Nested interrupt controller with 32 interrupts
■ Up to 28 external interrupts on 7 vectors
Timers
■ Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
LQFP32 7x7
VFQFPN32 5x5
■ 16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
■ 8-bit basic timer with 8-bit prescaler
■ Auto wake-up timer
■ 2 watchdog timers: Window watchdog and
independent watchdog
Communications interfaces
■ UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
■ SPI interface up to 8 Mbit/s
■ I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
■ 10-bit, ±1 LSB ADC with up to 7 multiplexed
channels + 1 internal channel, scan mode and
analog watchdog
I/Os
■ Up to 28 I/Os on a 32-pin package including 21
high sink outputs
■ Highly robust I/O design, immune against
current injection
■ Development support
– Embedded single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
April 2009
Doc ID 15590 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/88
www.st.com
1
1 page  
CR8F612X
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
CR8F612X access line features. . . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 14
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VFQFPN32/LQFP32 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CR8F612X alternate function remapping bits [7:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CR8F612X alternate function remapping bits [1:0] . . .... . . . . . . . . . . . . . . . . . . . . . . . . . 29
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 46
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 47
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 49
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 49
Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ADC accuracy with RAIN < 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Doc ID 15590 Rev 1
5/88
5 Page 
CR8F612X
4 Product overview
Product overview
The following section intends to give an overview of the basic features of the CR8F612X
functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1 Central processing unit CR8F
The 8-bit CR8F core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
● Harvard architecture
● 3-stage pipeline
● 32-bit wide program memory bus - single cycle fetching for most instructions
● X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
● 8-bit accumulator
● 24-bit program counter - 16-Mbyte linear memory space
● 16-bit stack pointer - access to a 64 K-level stack
● 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
● 20 addressing modes
● Indexed indirect addressing mode for look-up tables located anywhere in the address
space
● Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
● 80 instructions with 2-byte average instruction size
● Standard data movement and logic/arithmetic functions
● 8-bit by 8-bit multiplication
● 16-bit by 8-bit and 16-bit by 16-bit division
● Bit manipulation
● Data transfer between stack and accumulator (push/pop) with direct stack access
● Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 15590 Rev 1
11/88
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CR8F6125.PDF ] | |
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