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MAX6920AWP の電気的特性と機能

MAX6920AWPのメーカーはMaxim Integratedです、この部品の機能は「Serial-Interfaced VFD Tube Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 MAX6920AWP
部品説明 Serial-Interfaced VFD Tube Driver
メーカ Maxim Integrated
ロゴ Maxim Integrated ロゴ 




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MAX6920AWP Datasheet, MAX6920AWP PDF,ピン配置, 機能
MAX6920
12-Output, 76V, Serial-Interfaced VFD Tube Driver
General Description
The MAX6920 is a 12-output, 76V, vacuum fluo-
rescent display (VFD) tube driver that interfaces a
multiplexed VFD tube to a VFD controller such as the
MAX6850–MAX6853 or to a microcontroller. The
MAX6920 is also ideal for driving either static VFD tubes
or telecom relays.
Data is inputted using an industry-standard 4-wire serial
interface (CLOCK, DATA, LOAD, BLANK) for compatibil-
ity with both industry-standard drivers and Maxim’s VFD
controllers.
For easy display control, the active-high BLANK input
forces all driver outputs low, turning the display off, and
automatically puts the MAX6920 into shutdown mode.
Display intensity may also be controlled by pulse-width
modulating the BLANK input.
The MAX6920 has a serial interface data output pin,
DOUT, allowing any number of devices to be cascaded
on the same serial interface.
The MAX6920 is available in a 20-pin SO pack-
age. Maxim also offers VFD drivers with either 20
(MAX6921/MAX6931) or 32 outputs (MAX6922 and
MAX6932).
Applications
● White Goods
● Gaming Machines
● Avionics
● Industrial Weighing
● Security
● Telecom
Features
● 5MHz Industry-Standard 4-Wire Serial Interface
● 3V to 5.5V Logic Supply Range
● 8V to 76V Grid/Anode Supply Range
● Push-Pull CMOS High-Voltage Outputs
● Outputs can Source 40mA, Sink 4mA Continuously
● Outputs can Source 75mA Repetitive Pulses
● Outputs can be Paralleled for Higher Current Drive
● Any Output can be Used as a Grid or an Anode
Driver
● Blank Input Simplifies PWM Intensity Control
● Small 20-Pin SO Package
● -40°C to +125°C Temperature Range
Ordering Information
PART
MAX6920AWP
TEMP RANGE
-40°C to +125°C
PIN-PACKAGE
20 Wide SO
Pin Configuration
TOP VIEW
VBB 1
DOUT 2
OUT11 3
OUT10 4
OUT9 5 MAX6920AWP
OUT8 6
OUT7 7
OUT6 8
BLANK 9
GND 10
20 VCC
19 DIN
18 OUT0
17 OUT1
16 OUT2
15 OUT3
14 OUT4
13 OUT5
12 LOAD
11 CLK
Typical Operating Circuit
µC
VFDOUT
VFCLK
VFLOAD
VFBLANK
+5V
C1
100nF
+60V
C2
100nF
20
VCC
1
VBB
MAX6920
19 12
DIN OUT0 – OUT11
11
CLK
12
LOAD
9
BLANK
GND
10
19-3061; Rev 1; 8/14

1 Page





MAX6920AWP pdf, ピン配列
MAX6920
12-Output, 76V, Serial-Interfaced VFD Tube Driver
Electrical Characteristics (continued)
(Typical Operating Circuit, VBB = 8V to 76V, VCC = 3V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Rise Time OUT_ (20% to 80%)
tR VBB = 60V, CL = 50pF, RL = 2.3kW
Fall Time OUT_ (80% to 20%)
tF VBB = 60V, CL = 50pF, RL = 2.3kW
SERIAL INTERFACE TIMING CHARACTERISTICS
LOAD Rising to OUT_ Falling
Delay
(Notes 2, 3)
MIN TYP MAX
0.9 2
0.6 1.5
0.9 1.8
UNITS
µs
µs
µs
LOAD Rising to OUT_ Rising Delay
(Notes 2, 3)
1.2 2.4
µs
BLANK Rising to OUT_ Falling
Delay
(Notes 2, 3)
0.9
BLANK Falling to OUT_ Rising
Delay
(Notes 2, 3)
1.3
Input Leakage Current
CLK, DIN, LOAD, BLANK
IIH, IIL
0.05
Logic-High Input Voltage
CLK, DIN, LOAD, BLANK
Logic-Low Input Voltage
CLK, DIN, LOAD, BLANK
VIH
VIL
0.8 x
VCC
Hysteresis Voltage
DIN, CLK, LOAD, BLANK
DVI
0.6
High-Voltage DOUT
VOH
ISOURCE = -1.0mA
VCC
0.5
Low-Voltage DOUT
Rise and Fall Time DOUT
VOL ISINK = 1.0mA
CDOUT = 10pF
(Note 2)
3V to 4.5V
4.5V to 5.5V
60
30
CLK Clock Period
CLK Pulse-Width High
CLK Pulse-Width Low
CLK Rise to LOAD Rise Hold Time
DIN Setup Time
DIN Hold Time
tCP
tCH
tCL
tCSH
tDS
tDH
(Note 2)
3V to 4.5V
4.5V to 5.5V
200
90
90
100
5
20
15
DOUT Propagation Delay
tDO CDOUT = 10pF
3.0V to 4.5V
4.5V to 5.5V
25 120
20 75
LOAD Pulse High
tCSW
55
Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: Delay measured from control edge to when output OUT_ changes by 1V.
1.8
2.5
10
0.3 x
VCC
0.5
100
80
240
150
µs
µs
µA
V
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.maximintegrated.com
Maxim Integrated 3


3Pages


MAX6920AWP 電子部品, 半導体
MAX6920
12-Output, 76V, Serial-Interfaced VFD Tube Driver
VBB
SLEW- RATE
CONTROL
40
TYPICAL
OUT_
750
TYPICAL
Figure 2. MAX6920 CMOS Output Driver Structure
Detailed Description
The MAX6920 is a VFD tube driver comprising a
4-wire serial interface driving 12 high-voltage rail-to-rail
output ports. The driver is suitable for both static and
multiplexed displays.
The output ports feature high current-sourcing capabili-
ty to drive current into grids and anodes of static or
multiplex VFDs. The ports also have active current sink-
ing for fast discharge of capacitive display electrodes
in multiplexing applications.
The 4-wire serial interface comprises a 12-bit shift reg-
ister and a 12-bit transparent latch. The shift register is
written through a clock input CLK and a data input DIN
and the data propagates to a data output DOUT. The
data output allows multiple drivers to be cascaded and
operated together. The output latch is transparent to
the shift register outputs when LOAD is high, and latches
the current state on the falling edge of LOAD.
Each driver output is a slew-rated controlled CMOS push-
pull switch driving between VBB and GND. The output rise
time is always slower than the output fall time to avoid
shoot-through currents during output transitions. The
output slew rates are slow enough to minimize EMI, yet
are fast enough so as not to impact the typical 100µs digit
multiplex period and affect the display intensity.
Initial Power-Up and Operation
An internal reset circuit clears the internal registers of
the MAX6920 on power-up. All outputs OUT0 to OUT11
and the interface output DOUT initialize low regardless
of the initial logic levels of the CLK, DIN, BLANK, and
LOAD inputs.
4-Wire Serial Interface
The MAX6920 uses a 4-wire serial interface with three
inputs (DIN, CLK, LOAD) and a data output (DOUT).
This interface is used to write output data to the
MAX6920 (Figure 3) (Table 1). The serial interface data
word length is 12 bits, D0–D11.
The functions of the four serial interface pins are:
● CLK input is the interface clock, which shifts data into
the MAX6920’s 12-bit shift register on its rising edge.
● LOAD input passes data from the MAX6920’s 12-bit
shift register to the 12-bit output latch when LOAD
is high (transparent latch), and latches the data on
LOAD’s falling edge.
LOAD
CLK
DIN
tCL tCH
tDH
tDS
D11
D10
DOUT
Figure 3. 4-Wire Serial Interface Timing Diagram
tCSW
tCSH
tCP
D1
tDO
D0
D11
www.maximintegrated.com
Maxim Integrated 6

6 Page



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部品番号部品説明メーカ
MAX6920AWP

Serial-Interfaced VFD Tube Driver

Maxim Integrated
Maxim Integrated


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