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PDF UT54ACTS245E Data sheet ( Hoja de datos )

Número de pieza UT54ACTS245E
Descripción Octal Bus Transceiver
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



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UT54ACTS245E
Octal Bus Transceiver with Three-State Outputs
July 20013
www.aeroflex.com/Logic
Datasheet
FEATURES
Three-state outputs drive bus line directly
 m CRH CMOS process
- Latchup immune
High speed
Low power consumption
Wide power supply operating range of 3.0V to 5.5V
Available QML Q or V processes
Flexible package
 - 20-lead flatpack
UT54ACTS245E-SMD-5962-96573
DESCRIPTION
The UT54ACTS245E is a non-inverting octal bus transceiver
designed for asynchronous two-way communication between
data buses. The control function implementation minimizes
external timing requirements.
The device allows data transmission from the A bus to the B
bus or from the B bus to the A bus depending upon the logic
level at the direction control (DIR) input. The enable input (G)
disables the device so that the buses are effectively isolated.
The device is characterized over full HiRel temperature range
of -55C to +125C.
FUNCTION TABLE
ENABLE DIRECTION
G CONTROL DIR
OPERATION
L L B Data To A Bus
LH
A Data To B Bus
HX
Isolation
PINOUTS
DIR
A1
A2
A3
A4
A5
A6
A7
A8
VSS
20-Lead Flatpack
Top View
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
G
B1
B2
B3
B4
B5
B6
B7
B8
LOGIC SYMBOL
(19)
G
(1)
DIR
(2)
A1
(3)
A2
(4)
A3
(5)
A4
(6)
A5
(7)
A6
(8)
A7
(9)
A8
G3
3 EN1 (BA)
3 EN2 (AB)
1
2
(18)
B1
(17)
B2
(16)
B3
(15)
B4
(14)
B5
(13)
(12) B6
B7
(11)
B8
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
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UT54ACTS245E pdf
IOZH
Three-state output leakage cur-
rent, high
G = 5.5V; for all other inputs
VIN = VDD or VSS; VOUT = VDD
VDD = 5.5V
30 A
IOZL
Ptotal1
Ptotal2
IDDQ
IDDQ
CIN
COUT
Three-state output leakage cur-
rent, low
Power dissipation 2, 8
Power dissipation 2, 8
Quiescent Supply Current
Quiescent Supply Current
Delta
Input capacitance 5
Output capacitance 5
G = 5.5V; for all other inputs
VIN = VDD or VSS; VOUT = VSS
VDD = 5.5V
CL = 50pF
VDD = 4.5V to 5.5V
CL = 50pF
VDD = 3.0V to 3.6V
VIN = VDD or VSS
VDD from 3.0V to 5.5V
For input under test
VIN = VDD -2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
= 1MHz, VDD = 0V
= 1MHz, VDD = 0V
-30 A
1.5 mW/
MHZ
.75 mW/
MHZ
10 A
1.6 mA
15 pF
15 pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for the maximum radiation dose available for the respective device types.
8. Power does not include power contribution of any TTL output sink current.
9. Guaranteed by characterization, but not tested.
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