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UT54ACTS191 の電気的特性と機能

UT54ACTS191のメーカーはAeroflex Circuit Technologyです、この部品の機能は「Synchronous 4-Bit Up-Down Binary Counters」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54ACTS191
部品説明 Synchronous 4-Bit Up-Down Binary Counters
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT54ACTS191 Datasheet, UT54ACTS191 PDF,ピン配置, 機能
Standard Products
UT54ACS191/UT54ACTS191
Synchronous 4-Bit Up-Down Binary Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Single down/up count control line
‰ Look-ahead circuitry enhances speed of cascaded counters
‰ Fully synchronous in count modes
‰ Asynchronously presettable with load control
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS191 - SMD 5962-96564
‰ UT54ACTS191 - SMD 5962-96565
DESCRIPTION
The UT54ACS191 and the UT54ACTS191 are synchronous 4-
bit reversible up-down binary counters. Synchronous counting
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each other
when so instructed. Synchronous operation eliminates the out-
put counting spikes associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The di-
rection of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and when
D/U is high, it counts down.
The counters feature a fully independent clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occurs.
The counters are fully programmable. The outputs may be
preset to either logic level by placing a low on the load input
and entering the desired data at the data inputs. The output will
change to agree with the data inputs independently of the level
of the clock input. The asynchronous load allows counters to
be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (15) counting up.
PINOUTS
16-Pin DIP
Top View
B 1 16 VDD
QB 2 15 A
QA 3 14 CLK
CTEN 4 13 RCO
D/U 5 12 MAX/MIN
QC 6 11 LOAD
QD 7 10 C
VSS 8
9D
16-Lead Flatpack
Top View
B
QB
QA
CTEN
D/U
QC
QD
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
A
CLK
RCO
MAX/MIN
LOAD
C
D
The ripple clock output (RCO) produces a low-level output pulse
under those same conditions but only while the clock input is
low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for high-
speed operation.
The devices are characterized over full military temperature
range of -55°C to +125°C.
1

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UT54ACTS191 pdf, ピン配列
OPERATIONAL ENVIRONMENT1
PARAMETER
Total Dose
SEU Threshold 2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VDD
VI/O
TSTG
TJ
TLS
ΘJC
II
PD
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to VDD +.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD Supply voltage
4.5 to 5.5
V
VIN Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
°C
3


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UT54ACTS191 電子部品, 半導体
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
fMAX
tSU1
LOAD to Qn
LOAD to Qn
Data In to Qn
Data In to Qn
CLK to Qn
CLK to Qn
CLK to RCO
CLK to RCO
CLK to MAX/MIN
CLK to MAX/MIN
D/U to RCO
D/U to RCO
D/U to MAX/MIN
D/U to MAX/MIN
CTEN to RCO
CTEN to RCO
Maximum clock frequency
LOAD , CTEN, D/U
Setup time before CLK
2 20 ns
2 22 ns
2 23 ns
2 19 ns
2 17 ns
2 22 ns
2 12 ns
2 15 ns
2 22 ns
2 23 ns
2 16 ns
2 18 ns
2 15 ns
2 17 ns
2 12 ns
2 16 ns
63 MHz
12 ns
tSU2 A, B, C, D setup time before LOAD
tH1 CTEN and D/U hold time after CLK
tH23 A, B, C, D hold time after LOAD
tW Minimum pulse width
CLK high
CLK low
LOAD low
5
2
2
8
ns
ns
ns
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH2) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
6

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