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UT54ACTS163のメーカーはAeroflex Circuit Technologyです、この部品の機能は「4-Bit Synchronous Counters」です。 |
部品番号 | UT54ACTS163 |
| |
部品説明 | 4-Bit Synchronous Counters | ||
メーカ | Aeroflex Circuit Technology | ||
ロゴ | |||
このページの下部にプレビューとUT54ACTS163ダウンロード(pdfファイル)リンクがあります。 Total 10 pages
Standard Products
UT54ACS163/UT54ACTS163
4-Bit Synchronous Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Synchronously programmable
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS163 - SMD 5962-96554
UT54ACTS163 - SMD 5962-96555
DESCRIPTION
The UT54ACS163 and the UT54ACTS163 are synchronous
presettable 4-bit binary counters that feature internal carry look-
ahead logic for high-speed counting designs. Synchronous op-
eration occurs by having all flip-flops clocked simultaneously
so that the outputs change coincident with each other when in-
structed by the count-enable inputs and internal gating. A buff-
ered clock input triggers the four flip-flops on the rising (posi-
tive-going) edge of the clock input waveform.
The counters are fully programmable (i.e., they may be preset
to any number between 0 and 15). Presetting is synchronous;
applying a low level at the load input disables the counter and
causes the outputs to agree with the load data after the next clock
pulse.
The clear function is synchronous and a low level at the clear
input sets all four of the flip-flop outputs low after the next clock
pulse. This synchronous clear allows the count length to be mod-
ified by decoding the Q outputs for the maximum count desired.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, or LOAD) that modify the operat-
ing mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
PINOUTS
16-Pin DIP
Top View
CLR
CLK
A
B
C
D
ENP
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
RCO
QA
QB
QC
QD
ENT
LOAD
CLR
CLK
A
B
C
D
ENP
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
RCO
QA
QB
QC
QD
ENT
LOAD
LOGIC SYMBOL
(1)
CLR
(9)
LOAD
ENT
ENP
CLK
(10)
(7)
(2)
CTRDIV 16
5CT=0
M1
M2 3CT = 15
G3
G4
C5/2,3,4+
(3)
A
(4)
B
(5)
C
(6)
D
1,5D
(1)
(2)
(4)
(8)
(15) RCO
(14) QA
(13) QB
(12) QC
(11) QD
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-
cation 617-12.
1
1 Page OPERATIONAL ENVIRONMENT1
PARAMETER
Total Dose
SEU Threshold 2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
0.3 to 7.0
V
VI/O
TSTG
TJ
TLS
ΘJC
II
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
-.3 to VDD +.3
-65 to +150
+175
+300
20
±10
V
°C
°C
°C
°C/W
mA
PD
Maximum power dissipation
1W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
VIN
TC
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to VDD
-55 to + 125
UNITS
V
V
°C
3
3Pages AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
fMAX
tSU1
CLK to Qn
CLK to Qn
CLK to RCO
CLK to RCO
ENT to RCO
ENT to RCO
Maximum clock frequency
A, B, C, D
Setup time before CLK ↑
4 24 ns
4 22 ns
4 22 ns
4 24 ns
1 13 ns
1 14 ns
77 MHz
6 ns
tSU2 LOAD, ENP, ENT, CLR low or high
Setup time before CLK↑
tH13 Data hold time after CLK ↑
tH2 All synchronous inputs hold time after CLK ↑
tW Minimum pulse width
CLR low
CLK high
CLK low
6
1
1
7
ns
ns
ns
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
3. Based on characterization, hold time (tH1) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested.
6
6 Page | |||
ページ | 合計 : 10 ページ | ||
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PDF ダウンロード | [ UT54ACTS163 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
UT54ACTS163 | 4-Bit Synchronous Counters | Aeroflex Circuit Technology |
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