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UT54ACS74 の電気的特性と機能

UT54ACS74のメーカーはAeroflex Circuit Technologyです、この部品の機能は「Dual D Flip-Flops」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT54ACS74
部品説明 Dual D Flip-Flops
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT54ACS74 Datasheet, UT54ACS74 PDF,ピン配置, 機能
Standard Products
UT54ACS74/UT54ACTS74
Dual D Flip-Flops with Clear & Preset
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 14-pin DIP
- 14-lead flatpack
‰ UT54ACS74 - SMD 5962-96534
‰ UT54ACTS74 - SMD 5962-96535
DESCRIPTION
The UT54ACS74 and the UT54ACTS74 contain two indepen-
dent D-type positive triggered flip-flops. A low level at the
Preset or Clear inputs sets or resets the outputs regardless of the
levels of the other inputs. When Preset and Clear are inactive
(high), data at the D input meeting the setup time requirement
is transferred to the outputs on the positive-going edge of the
clock pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels at the outputs.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
INPUTS
CLR
CLK
HX
LX
LX
H
H
HL
OUTPUT
D QQ
XHL
X LH
X H1 H1
HHL
L LH
X Qo Qo
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum
levels for VOH if the lows at preset and clear are near VIL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS
14-Pin DIP
Top View
CLR1
D1
CLK1
PRE1
Q1
Q1
VSS
1 14
2 13
3 12
4 11
5 10
69
78
VDD
CLR2
D2
CLK2
PRE2
Q2
Q2
14-Lead Flatpack
Top View
CLR1
D1
CLK1
PRE1
Q1
Q1
VSS
1 14
2 13
3 12
4 11
5 10
69
78
VDD
CLR2
D2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
(4)
PRE1
(3)
CLK1
(2)
D1
(1)
CLR1
(10)
PRE2
(11)
CLK2
(12)
D2
(13)
CLR2
S
C1
D1
R
(5) Q1
(6) Q1
(9) Q2
(8) Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1

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UT54ACS74 pdf, ピン配列
OPERATIONAL ENVIRONMENT1
PARAMETER
Total Dose
SEU Threshold 2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
VI/O
TSTG
TJ
TLS
ΘJC
II
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
-0.3 to 7.0
-.3 to VDD +.3
-65 to +150
+175
+300
20
±10
V
V
°C
°C
°C
°C/W
mA
PD Maximum power dissipation
1W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
VIN
TC
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to VDD
-55 to + 125
UNITS
V
V
°C
3


3Pages


UT54ACS74 電子部品, 半導体
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL
tPLH
tPLH
tPHL
tPHL
tPLH
fMAX
tSU1
tSU2
tH3
tW
CLK to Q, Q
CLK to Q, Q
PRE to Q
PRE to Q
CLR to Q
CLR to Q
Maximum clock frequency
PRE or CLR inactive
Setup time before CLK
Data setup time before CLK
Data hold time after CLK
Minimum pulse width
PRE or CLR low
CLK high
CLK low
3 21 ns
1 20 ns
1 15 ns
3 19 ns
3 19 ns
1 15 ns
71 MHz
5 ns
5 ns
2 ns
7 ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
6

6 Page



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共有リンク

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部品番号部品説明メーカ
UT54ACS74

Radiation-Hardened Dual D Flip-Flops with Clear & Preset

Aeroflex Microelectronic Solutions
Aeroflex Microelectronic Solutions
UT54ACS74

Radiation-Hardened Dual D Flip-Flops

ETC
ETC
UT54ACS74

Dual D Flip-Flops

Aeroflex Circuit Technology
Aeroflex Circuit Technology


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