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MMSF5N02HDR2のメーカーはON Semiconductorです、この部品の機能は「Power MOSFET ( Transistor )」です。 |
部品番号 | MMSF5N02HDR2 |
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部品説明 | Power MOSFET ( Transistor ) | ||
メーカ | ON Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとMMSF5N02HDR2ダウンロード(pdfファイル)リンクがあります。 Total 10 pages
MMSF5N02HD
Preferred Device
Power MOSFET
5 Amps, 20 Volts
N−Channel SO−8
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc−dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for SO−8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage − Continuous
Drain Current − Continuous @ TA = 25°C
Drain Current − Continuous @ TA = 100°C
Drain Current − Single Pulse (tp ≤ 10 μs)
Total Power Dissipation @ TA = 25°C
(Note 1.)
VDSS
VDGR
VGS
ID
ID
IDM
PD
20 Vdc
20 Vdc
± 20 Vdc
8.2 Adc
5.6
41 Apk
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg
− 55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak
IL = 15 Apk, L = 6.0 mH, RG = 25 Ω)
Thermal Resistance − Junction to Ambient
(Note 1.)
EAS
RθJA
675 mJ
50 °C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
260 °C
1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),
10 sec. max.
http://onsemi.com
5 AMPERES
20 VOLTS
RDS(on) = 25 mW
N−Channel
D
G
S
MARKING
DIAGRAM
SO−8
8
CASE 751
STYLE 13
1
S5N02
LYWW
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
N−C
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
ORDERING INFORMATION
Device
Package
Shipping
MMSF5N02HDR2 SO−8 2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 7
1
Publication Order Number:
MMSF5N02HD/D
1 Page MMSF5N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10
VGS = 10 V
8 4.5 V
3.8 V
6
TJ = 25°C
3.1 V
4
2
2.4 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
2
10
VDS ≥ 10 V
8
6
4
TJ = 100°C
2 25°C
− 55°C
0
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
3.3
0.2
ID = 2.5 A
0.16
0.12
0.023
TJ = 25°C
0.021
VGS = 4.5 V
0.08
0.019
10 V
0.04
0
0 1 2 3 4 5 6 7 8 9 10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
0.017
0 2 4 6 8 10
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
VGS = 10 V
1.4 ID = 2.5 A
1.2
1
0.8
1000
VGS = 0 V
100
10
TJ = 125°C
100°C
25°C
0.6
−50
−25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
150
1
0 4 8 12 16 20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
3Pages MMSF5N02HD
di/dt = 300 A/μs
Standard Cell Density
trr
High Cell Density
trr
ta
tb
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
100
VGS = 10 V
SINGLE PULSE
10 TC = 25°C
100 μs
1 ms
10 ms
1 dc
RDS(on) LIMIT
0.1
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided), 10s max.
0.01
0.1 1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
100
675
ID = 15 A
575
475
375
275
175
75
−25
25
50 75 100 125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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部品番号 | 部品説明 | メーカ |
MMSF5N02HDR2 | Power MOSFET ( Transistor ) | ON Semiconductor |