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PDF MD1822K6-G Data sheet ( Hoja de datos )
| Número de pieza | MD1822K6-G | |
| Descripción | High Speed Four Channel MOSFET Driver | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Supertex inc.
MD1822
High Speed Four Channel MOSFET Driver with Two Inverting
and Two Non-Inverting Outputs
Features
►► Mixed inversion MOSFET driver
►► 6.0ns rise and fall time
►► 2.0A peak output source/sink current
►► 1.8 to 5.0V input CMOS compatible
►► 5.0 to 10V total supply voltage
►► Smart logic threshold
►► Low jitter design
►► Four matched channels
►► Drives two P- and two N-channel MOSFETs
►► Outputs can swing below ground
►► Low inductance, quad flat no-lead package
►► High performance, thermally enhanced
packaging
Applications
►► Medical ultrasound imaging
►► Piezoelectric transducer drivers
►► Non-Destructive Testing (NDT)
►► PIN diode driver
►► CCD Clock driver/buffer
►► High speed level translator
General Description
The Supertex MD1822 is a high speed, four channel MOSFET driver
designed to drive high voltage P- and N-channel MOSFETs for medical
ultrasound applications and other applications requiring a high output
current for a capacitive load. The high-speed input stage of the MD1822
can operate from a 1.8 to 5.0V logic interface with an optimum operating
input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to
set the level translator switch threshold to the average of the input logic 0
and logic 1 levels. The input logic levels may be ground referenced, even
though the driver is putting out bipolar signals. The level translator uses a
proprietary circuit, which provides DC coupling together with high-speed
operation.
The output stage of the MD1822 has separate power connections
enabling the output signal L and H levels to be chosen independently from
the supply voltages used for the majority of the circuit. As an example, the
input logic levels may be 0 and 1.8V, the control logic may be powered by
+5.0 and -5.0V, and the output L and H levels may be varied anywhere
over the range of -5.0 to +5.0V. The output stage is capable of peak
currents of up to ±2.0A, depending on the supply voltages used and load
capacitance present. The PE pin serves a dual purpose. First, its logic H
level is used to compute the threshold voltage level for the channel input
level translators. Second, when PE is low, the outputs are disabled, with
the A & C output high and the B & D output low. This assists in properly
precharging the AC coupling capacitors that may be used in series in the
gate drive circuit of an external PMOS and NMOS transistor pair.
Typical Application Circuit
+10V
+10V
0.1µF
+3.3V
Supertex
MD1822
0.47µF
PE VDD
VH
10nF
3.3V CMOS
Logic Inputs
PIN INA
INB
NIN
OUTA
OUTB
10nF
DMP INC
OUTC
Supertex
TC6320
+100V
0.47µF
-100V
0.47µF
HVOUT
IND
GND
VSS
OUTD
VL
10nF
10nF
Supertex
TC6320
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page  
MD1822
Timing Diagram
VTH / VPE Curve
VTH vs VPE
3.3V
IN
0V
10V
OUT
0V
50%
50%
tPLH
90%
10%
tr
tPHL
90%
10%
tf
2.0
1.5
VTH
1.0
VPE/2
0.5
0
0 1.0 2.0 3.0 4.0 5.0
VPE
Application Information
For proper operation of the MD1822, low inductance bypass
capacitors should be used on the various supply pins. The
GND pin should be connected to the logic ground. The INA,
INB, INC, IND, and PE pins should be connected to a logic
source with a swing of GND to PE, where PE is 1.8 to 5.0V.
Good trace practices should be followed corresponding to
the desired operating speed. The internal circuitry of the
MD1822 is capable of operating up to 100MHz, with the
primary speed limitation being the loading effects of the load
capacitance. Because of this speed and the high transient
currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible.
Unless the load specifically requires bipolar drive, the VSS
and VL pins should have low inductance feed-through
connections directly to a ground plane. If these voltages
are not zero, then they need bypass capacitors in a manner
similar to the positive power supplies. The power connection
VDD should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to prevent
resonance in the powerleads.
The voltages of VH and VL decide the output signal levels.
These two pins can draw fast transient currents of up to
2.0A, so they should be provided with an appropriate bypass
capacitor located next to the chip pins. A ceramic capacitor
of up to 1.0µF may be appropriate, with a series ferrite bead
to prevent resonance in the power supply lead coming to
the capacitor. Pay particular attention to minimizing trace
lengths, current loop area and using sufficient trace width to
reduce inductance. Surface mount components are highly
recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small
series resistance in series with the output signal to obtain
better waveform transitions at the load terminals. This will of
course reduce the output voltage slew rate at the terminals
of a capacitive load.
Pay particular attention that parasitic couplings are minimized
from the output to the input signal terminals. The parasitic
feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 1.8V even small coupled
voltages may cause problems. Use of a solid ground plane
and good power and signal layout practices will prevent this
problem. Be careful that a circulating ground return current
from a capacitive load cannot react with common inductance
to cause noise voltages in the input logic circuitry.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
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| PDF Descargar | [ Datasheet MD1822K6-G.PDF ] | |
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