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PDF HV5122PG-G Data sheet ( Hoja de datos )

Número de pieza HV5122PG-G
Descripción 32-Channel Serial to Parallel Converter
Fabricantes Supertex 
Logotipo Supertex Logotipo



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No Preview Available ! HV5122PG-G Hoja de datos, Descripción, Manual

Supertex inc.
HV5122
32-Channel Serial to Parallel Converter
With Open Drain Outputs
Features
Processed with HVCMOS® technology
Output voltages to 225V using a ramped
supply voltage
SINK current minimum 100mA
Shift register speed 8.0MHz
Strobe and enable inputs
CMOS compatible inputs
Forward and reverse shifting options
Hi-Rel processing available
General Description
The HV5122 is a low voltage serial to high voltage parallel converter
with open drain outputs. This device has been designed for use as a
driver for AC electroluminescent displays. They can also be used in
any application requiring multiple output high voltage current sinking
capabilities such as driving inkjet and electrostatic print heads,
plasma panels, vacuum fluorescent, or large matrix LCD displays.
This device consists of a 32-bit shift register and control logic to
perform the Output Enable and all-on functions. Data is shifted
through the shift register on the high to low transition of the clock.
The HV5122 shifts in the counter-clockwise direction when viewed
from the top of the package. A data output buffer is provided for
cascading devices. This output reflects the current status of the last
bit of the shift register. Operation of the shift register is not affected
by the OE(Output Enable) or the STR(Strobe) inputs.
The HV5122 has been designed to be used in systems which either
switch off the high voltage supply before changing the state of the
high voltage outputs or which limit the current through each output.
Functional Block Diagram
STR
OE
DATA
INPUT
CLK
32 bit
Static Shift
Register
HVOUT1
HVOUT2
28 Additional
Outputs
HVOUT31
HVOUT32
Data Out
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

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HV5122PG-G pdf
HV5122
44-Lead PQFP Pin Assignment (PG)
HV5122PG
Pin
Function
Description
1 HVOUT11
2 HVOUT12
3 HVOUT13
4 HVOUT14
5 HVOUT15
6 HVOUT16
7 HVOUT17
8 HVOUT18
9 HVOUT19
10 HVOUT20
11
HVOUT21
High voltage outputs.
12 HVOUT22
13 HVOUT23
14 HVOUT24
15 HVOUT25
16 HVOUT26
17 HVOUT27
18 HVOUT28
19 HVOUT29
20 HVOUT30
21 HVOUT31
22 HVOUT32
23 DATA OUT Data output for cascading to the data input of the next device.
24
25
N/C No connect.
26
27
Output enable input.
28 OE When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in
each channel. When OE is HIGH, all HV outputs reflect data latched.
29
CLK
Data shift register clock. Input are shifted into the shift register on the positive edge of
the clock.
30
GND
Logic and high voltage ground.
31
VDD
Low voltage logic power rail.
32
STR
Strobe.
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
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