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PI6C49003A の電気的特性と機能

PI6C49003AのメーカーはPericom Semiconductorです、この部品の機能は「Gen 2 Networking Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI6C49003A
部品説明 Gen 2 Networking Clock Generator
メーカ Pericom Semiconductor
ロゴ Pericom Semiconductor ロゴ 




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PI6C49003A Datasheet, PI6C49003A PDF,ピン配置, 機能
PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal
• Five PCIe® Gen. 2 100MHz HCSL outputs with optional
-0.5% spread spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
Description
The PI6C49003A is a clock generator device intended for PCIe®
Gen2 networking applications. The device includes five 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe Gen
2, two single-ended 50MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133MHz output.
Using a serially programmable SMBUS interface, the PI6C49003A
incorporates spread spectrum modulation on the twelve 100MHz
HCSL PCIe Gen 2 outputs, and independent frequency margining
on the 50MHz output, 33.3333MHz and 66.6666MHz clock
outputs.
Block Diagram
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
VDD
14
SCLK
SDATA
PD_RESET
PLL, Dividers,
Buffers, and
Logic
5
10
GND
ISET
475 Ohms
1%
Pin Configuration
100M_OUT(0-4)
50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
VDD
IREF
NC
NC
VDD
VDD
GND
GND
VDD
GND
VDD
SCLK
SDATA
GND
50M_Out1
50M_Out2
VDD
GND
VDD
32.256M_Out1
GND
NC
NC
PD_RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 VDD
46 100M_Q0-
45 100M_Q0+
44 100M_Q1+
43 100M_Q1-
42 VDD
41 GND
40 VDD
39 100M_Q2+
38 100M_Q2-
37 100M_Q3+
36 100M_Q3-
35 VDD
34 GND
33 VDD
32 100M_Q4+
31 100M_Q4-
30 33/66/133M_Out1
29 VDD
28 GND
27 VDD
26 X2
25 X1
All trademarks are property of their respective owners.
14-0198
1
www.pericom.com 11/11/14

1 Page





PI6C49003A pdf, ピン配列
Pin Description (Cont..)
Pin # Pin Name
Pin Type Pin Description
33 VDD
34 GND
35 VDD
36 100M_Q3-
37 100M_Q3+
38 100M_Q2-
39 100M_Q2+
40 VDD
41 GND
42 VDD
43 100M_Q1-
44 100M_Q1+
45 100M_Q0+
46 100M_Q0-
47 VDD
48 GND
Power
Power
Power
Output
Output
Output
Output
Power
Power
Power
Output
Output
Output
Output
Power
Power
3.3V Supply Pin
Ground
3.3V Supply Pin
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
Ground
3.3V Supply Pin
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
Ground
PI6C49003A
PCIe® Gen 2 Networking Clock Generator
All trademarks are property of their respective owners.
14-0198
3
www.pericom.com 11/11/14


3Pages


PI6C49003A 電子部品, 半導体
PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
0
1
1
Bit 5
X
0
1
Description
(PD_RESET = "H" will enable all outputs; SMBus cannot control each output.)
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
Enable outputs according to the SMBus default values; SMBus can control each output.
PD_RESET HW pin/signal = DON'T CARE
Byte 1: Control Register
Bit Description
Type
Power Up Con-
dition
Output(s) Affected
Notes
7 OE for 32.256M_Out1
RW 1
32.256M_Out1
0 = disabled
1 = enabled
6 OE for 50M_Out1
RW 1
50M_Out1
0 = disabled
1 = enabled
5 OE for 33/66/133M_Out1
RW 1
33/66/133M_Out1
0 = disabled
1 = enabled
4
OE for 100M_Q11 HCSL output
RW
1
100M_Q11
0 = disabled
1 = enabled
3
OE for 100M_Q10 HCSL output
RW
0
100M_Q10
0 = disabled
1 = enabled
2 OE for 100M_Q09 HCSL output RW 0
100M_Q9
0 = disabled
1 = enabled
1 OE for 100M_Q08 HCSL output RW 0
100M_Q8
0 = disabled
1 = enabled
0
OE for 100M_Q07 HCSL output
RW
0
100M_Q7
0 = disabled
1 = enabled
Byte 2: Control Register
Bit
7
6
5
4 to 0
Description
Frequency margining select bit FS6
Frequency margining select bit FS5
Frequency margining select bit FS4
Reserved
Type
RW
RW
RW
R
Power Up Con-
dition
1
0
0
Undefined
Output(s) Affected
33/66/133M_Out1
Not Applicable
Notes
See 33/66/133MHz
Frequency Margin-
ing Table on Page 3
All trademarks are property of their respective owners.
14-0198
6
www.pericom.com 11/11/14

6 Page



ページ 合計 : 12 ページ
 
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共有リンク

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部品番号部品説明メーカ
PI6C49003

Networking Clock Generator

Pericom Semiconductor
Pericom Semiconductor
PI6C49003A

Gen 2 Networking Clock Generator

Pericom Semiconductor
Pericom Semiconductor


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