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PDF PI6C49003 Data sheet ( Hoja de datos )

Número de pieza PI6C49003
Descripción Networking Clock Generator
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI6C49003 Hoja de datos, Descripción, Manual

PI6C49003
Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal such as Saronix-eCera™ SRX7278
• Five PCIe® 100MHz outputs with optional -0.5% spread
spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
Description
The PI6C49003 is a clock generator device intended for PCIe®/
networking applications. The device includes ve 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe,
two single-ended 50 MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133 MHz output.
Using a serially programmable SMBUS interface, the PI6C49003
incorporates spread spectrum modulation on the ve 100 MHz
HCSL PCIe outputs, and independent frequency margining on the
50MHz output, 33.3333MHz and 66.6666MHz clock outputs.
Pin Conguration
Block Diagram
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
VDD
14
SCLK
SDATA
PD_RESET
PLL, Dividers,
Buffers, and
Logic
5
100M_OUT(0-4)
50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
10
GND
ISET
475 Ohms
1%
VDD
IREF
NC
NC
VDD
VDD
GND
GND
VDD
GND
VDD
SCLK
SDATA
GND
50M_Out1
50M_Out2
VDD
GND
VDD
32.256M_Out1
GND
NC
NC
PD_RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
09-0097
1
48 GND
47 VDD
46 100M_Q0-
45 100M_Q0+
44 100M_Q1+
43 100M_Q1-
42 VDD
41 GND
40 VDD
39 100M_Q2+
38 100M_Q2-
37 100M_Q3+
36 100M_Q3-
35 VDD
34 GND
33 VDD
32 100M_Q4+
31 100M_Q4-
30 33/66/133M_Out1
29 VDD
28 GND
27 VDD
26 X2
25 X1
PS9023A
11/20/09

1 page




PI6C49003 pdf
PI6C49003
Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6 Bit 5 Description
0 X PD_RESET HW pin/signal = enabled
1 0 Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
1 1 Enable all outputs, PD_RESET HW pin/signal = DON'T CARE
Byte 1: Control Register
Bit Description
7 OE for 32.256M_Out1
6 OE for 50M_Out1
5
4
3 to 0
OE for 33/66/133M_Out1
Reserved
Reserved
Type
RW
RW
RW
RW
RW
Power Up Condi-
tion
Output(s) Affected
1 32.256M_Out1
1 50M_Out1
1 33/66/133M_Out1
1 Not Applicable
0 Not Applicable
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 2: Control Register
Bit Description
Type
7
6
5
4 to 0
Frequency margining select bit FS6
Frequency margining select bit FS5
Frequency margining select bit FS4
Reserved
RW
RW
RW
R
Power Up Condi-
tion
Output(s) Affected
1
0 33/66/133M_Out1
0
Undened
Not Applicable
Notes
See 33/66/100MHz
Frequency Select
Table on Page 3
Byte 3: Control Register
Bit Description
7 OE for 100M_Q4 HCSL Output
5 OE for 100M_Q3 HCSL Output
4 OE for 100M_Q2 HCSL Output
2 OE for 100M_Q1 HCSL Output
1 OE for 100M_Q0 HCSL Output
3, 6 Reserved
0 Reserved
09-0097
Type
RW
RW
RW
RW
RW
RW
R
Power Up Con-
dition
Output(s) Affected
0 100M_Q4
0 100M_Q3
0 100M_Q2
1 100M_Q1
1
0
Undened
100M_Q0
Not Applicable
Not Applicable
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
5
PS9023A
11/20/09

5 Page





PI6C49003 arduino
Conguration test load board termination for HCSL Outputs
PI6C49003
Networking Clock Generator
PI6C49003
Rs
337
5%
Rs
337
5%
4757
1%
Rp
49.97
1%
TLA
Rp
49.97
1%
TLB
2pF
5%
Clock
Clock#
2pF
5%
Figure 4. Conguration Test Load Board Termination
09-0097
11
PS9023A
11/20/09

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