PDF PI6C49019 Data sheet ( Hoja de datos )

Número de pieza	PI6C49019
Descripción	Low Power Networking Clock Generator
Fabricantes	Pericom Semiconductor
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No Preview Available ! PI6C49019 Low Power Networking Clock Generator Features ÎÎ3.3V supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎOutput • 4x100MHz HCSL PCIe clock outputs with integrated series termination resistors, spread spectrum capability ospnreaalld1.00MHz PCIe clock outputs with -0.5% down • 1x single-ended 33.33MHz or 67.33MHz output with spread spectrum capability • 1x single-ended 125MHz output for Gigabit Ethernet • 1x single-ended 25MHz • 1x single-ended 48MHz • 1x single-ended 19.2MHz ÎÎPackaging (Pb free and Green) : 48-pin TSSOP (A) ÎÎIndustrial temperature support Block Diagram Description The new PI6C49019 is a high integration clock generator intended for all kinds of embedded applications and networking application with PCIe interface. The device is the most cost effective way to generate multi-frequencies and multi-outputs clocks from a 25MHz crystal and reference clock. The device can generate four pairs low power 100MHz HCSL outputs for PCIe, one single-ended 25MHz and 125 MHz output, one single-ended 48MHz and 19.2 MHz output, and one single-ended 33.33 MHz or 67.33MHz output with spread spectrum. Using a serially programmable SMBus interface, the PI6C49019 incorporates spread spectrum modulation on the four 100 MHz PCI-Express outputs with -0.5% down spread and the 33.33 MHz/67.33 MHz output with down spread. VDD VDDO2 SCLK SDATA PD_RESET PLL Clock Synthesis, Dividers, Buffers and Configuration Logic X1/ICLK 25 MHz crystal or clock input X2 Clock Buffer/ Crystal Oscillator External caps required with crystal for accurate tuning of the clock GND 100 MHz PCIE0 100 MHz PCIE1 100 MHz PCIE2 100 MHz PCIE3 25 MHz 125 MHz/REF 33.33 MHz/67.33 MHz 48 MHz 19.2 MHz 13-0103 1 www.pericom.com PI6C49019 Rev. B 06/25/13 1 page PI6C49019 Low Power Networking Clock Generator Serial Data Interface (SMBus) PI6C49019 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad- dress and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits Start bit D2H Ack Register offset Ack Byte Count = N Ack Data Byte 0 Ack … Data Byte N-1 Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 1 Ack 1 bit Stop bit How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits S: M: send M: M: S: starting Start Send sends databyte bit "D2h" Ack location: N S: sends Ack M: Start bit M: Send "D3h" S: sends Ack sends # of data bytes that will be sent: M: sends Ack S: sends start- ing data byte N X 1 bit M: sends Ack … … 8 bits S: sends data byte N+X- 1 1 bit M: Not Ac- knowl- edge 1 bit M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description 7 Spread Select for 100MHz HCSL PCI-Express clocks 6 Enables hardware or software control of OE bits (see Byte 0-Bit 6 and Bit 5 Functionality table) Software PD_RESET bit. Enables or disables all 5 outputs. (see Byte 0-Bit 6 and Bit 5 Functionality table) 4 Spread Select for 33.33/67.33 MHz S1 3 Spread Select for 33.33/67.33 MHz Page 4 S0 2 OE for single-ended 25 MHz 1 Frequency Select Bit 0 OE for single-ended 125 MHz/REF 13-0103 Type RW RW RW RW RW RW RW RW 5 Power Up Condition 0 Output(s) Affected All 100MHz HCSL PCI-Express outputs 0 PD_RESET, bit 5 1 All outputs Notes 0=spread off 1=-0.5% down 0 = hardware cntl 1 = software ctrl 0 = disabled 1 = enabled 0 33MHz LVCMOS output See Table1 on Page4 0 pin 15 1 25M 0 = disabled 1 = enabled 1 125M/REF 0 = REF 1 = 125M 1 Single-ended 125MHz/REF pin 30 0 = disabled 1 = enabled www.pericom.com PI6C49019 Rev. B 06/25/13 5 Page PI6C49019 Low Power Networking Clock Generator Notes (Continued) 7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation. 8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–. 9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. 10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread. 11. Matching applies to rising edge rate for PCIe and falling edge rate for PCIeN. It is measured using a ±75 mV window centered on the median cross point where PCIe rising meets PCIeN falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rising edge rate of PCIe should be compared to the falling edge rate of PCIeN. The maximum allowed difference should not exceed 20% of the slowest edge rate. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Thermal Resistance Junction to Top of Case Symbol θJA θJA θJA θJC ΨJT ΨJT ΨJT Conditions Still air 1 m/s air flow 3 m/s air flow Still air 1 m/s air flow 3 m/s air flow Min. Typ. Max. Units 60.3 °C/W 53 °C/W 50 °C/W 27.7 °C/W 1.2 °C/W 1.5 °C/W 2.0 °C/W 13-0103 11 www.pericom.com PI6C49019 Rev. B 06/25/13 11 Page

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