PDF PI6C49016 Data sheet ( Hoja de datos )

Número de pieza	PI6C49016
Descripción	Low Power Networking Clock Generator
Fabricantes	Pericom Semiconductor
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No Preview Available ! PI6C49016 Low Power Networking Clock Generator Features ÎÎ25 MHz crystal or clock input ÎÎThree differential 100 MHz PCI-Express clock outputs – push-pull termination ÎÎSpread spectrum capability on all 100 MHz PCI-e clock outputs with -0.5% down spread ÎÎOne single-ended 66.66 MHz output ÎÎOne single-ended 125 MHz output for Gigabit Ethernet at 2.5V ÎÎOne single-ended 80 MHz output with selectable down spread. ÎÎ40-pin QFN package ÎÎOperating voltage 3.3 V ±5% ÎÎIndustrial temperature (-40 to +85°C) Description The PI6C49016 is a clock generator device intended for PCI- Express/networking applications. The device includes three 100 MHz differential outputs for PCI-Express using reduced power, one single-ended 125 MHz output, one single-ended 66.66 MHz, and one single-ended 80 MHz output with spread spectrum. Using a serially programmable SMBus interface, the PI6C49016 incorporates spread spectrum modulation on the four 100 MHz PCI-Express outputs with -0.5% down spread and the 80 MHz output with selectable down spread. Block Diagram VDD VDDO SCLK SDATA PD_RESET X1/CLK 25 MHz X2 External caps required with crystal for accurate tuning of the clock Clock Buffer/ Crystal Ocsillator 13-0102 PLL1 with SS PLL2 PLL3 with SS PLL4 100MHz PCI-Express 0 100MHz PCI-Express 1 100MHz PCI-Express 2 125MHz (2.5V) 80MHz 66.66MHz GND 1 www.pericom.com PI6C49016 Rev. B 06/25/13 1 page PI6C49016 Low Power Networking Clock Generator Serial Data Interface (SMBus) PI6C49016 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad- dress and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Note: 1. D2H Ack Register offset Ack Byte Count =N Ack Data Byte 0 Ack … Data Byte N-1 Ack Stop bit Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit M: send M: M: S: starting S: M: Start Send sends databyte sends Start bit "D2h" Ack location: Ack bit N 8 bits M: Send "D3h" 1 bit S: sends Ack 8 bits S: sends # of data bytes that will be sent: X 1 bit M: sends Ack 8 bits S: sends start- ing data byte N 1 bit … 8 bits 1 bit S: M: M: sends Not sends … data Ac- Ack byte knowl- N+X-1 edge 1 bit M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description 7 Spread Select for 100 MHz push-pull PCI-Express clocks 6 Reserved 5 Global PD_RESET bit. Enables or disables all outputs. 4 Spread Select for 80MHz S1 3 Spread Select for 80MHz S0 2 OE for 66.66 MHz output 1 Reserved 0 OE for single-ended 125MHz Type RW R RW RW RW RW R RW Power Up Condition 0 - 1 0 1 1 - 1 Output(s) Affected All 100MHz PCI- Express outputs - All outputs Notes 0=spread off 1 = -0.5% down spread - 0 = disabled 1 = enabled 80M See Table 1 on Page4 66.66M - Single-ended 125MHz 0 = disabled 1 = enabled - 0 = disabled 1 = enabled 13-0102 5 www.pericom.com PI6C49016 Rev. B 06/25/13 5 Page PI6C49016 Low Power Networking Clock Generator Notes (Continued) 7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation. 8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–. 9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. 10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread. 11. Matching applies to rising edge rate for PCIe and falling edge rate for PCIeN. It is measured using a ±75 mV window centered on the median cross point where PCIe rising meets PCIeN falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rising edge rate of PCIe should be compared to the falling edge rate of PCIeN. The maximum allowed difference should not exceed 20% of the slowest edge rate. 13-0102 11 www.pericom.com PI6C49016 Rev. B 06/25/13 11 Page

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