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PDF PI6C49015 Data sheet ( Hoja de datos )

Número de pieza PI6C49015
Descripción Embedded Clock Generator
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI6C49015 Hoja de datos, Descripción, Manual

PI6C49015
Embedded Clock Generator
Features
ÎÎ3.3V ±10% supply voltage
ÎÎ25MHz XTAL or reference clock input
ÎÎFive PCIe® 2.0 Compliant 100MHz selectable HCSL outputs
with -0.5% spread
– default is spread off
ÎÎTwo 25MHz LVCMOS output
ÎÎIndustrial temperature range: -40°C to 85°C
ÎÎ Packaging (Pb free and Green)
àà TSSOP 28 (L)
Description
The PI6C49015 is a high performance networking clock
generator which generates PCIe 2.0 Compliant 100MHz HCSL
clock signals along with two LVCMOS 25MHz clock from either
25MHz crystal or reference input. This integrated solution is
ideal for Networking, Embedded systems and other systems that
require PCIe 1.0 and 2.0 HCSL signals and 25MHz clocks yet
small foot print.
Applications
ÎÎNetworking systems
ÎÎEmbedded systems
ÎÎOther systems
Block Diagram
Pin Configuration
X1/REFIN
X2
Crystal
Ocillator
PLL Clock Synthesis
& Spread Spectrum
& Control Circuit
SCLK
SDATA
475IROEFhm
100MHz
5
Q_25M
2
IREF
100M_Q4-
100M_Q4+
100M_Q3-
100M_Q3+
SCLK
SDATA
GND_25M
25M_OUT1
25M_OUT2
VDD_25M
GND_XTAL
PDRESET
X1
O
GND0_100M
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDDA
GNDA
VDDO_100M
VDDO_100M
GNDO_100M
100M_Q2+
100M_Q2-
VDD_XTAL
X2
12-0168
1 www.pericom.com
P-0.1
02/29/12

1 page




PI6C49015 pdf
Byte 3: Control Register
Bit Description
7 OE for 100M_Q2 HCSL Output
6 to 3 Reserved
2 OE for 100M_Q1 HCSL Output
1 OE for 100M_Q0 HCSL Output
0 Reserved
PI6C49015
Embedded Clock Generator
Type
RW
RW
RW
RW
R
Power Up
Condition
1
Undefined
1
1
Undefined
Output(s) Affected
100M_Q2
Not Applicable
100M_Q1
100M_Q0
Not Applicable
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
Byte 4 & 5: Control Register
Bit
7 to 0
Description
Reserved
Type
R
Power Up Con-
dition
Undefined
Output(s) Affected
Not Applicable
Notes
Byte 6: Control Register
Bit Description
7 Revision ID bit 3
6 Revision ID bit 2
5 Revision ID bit 1
4 Revision ID bit 0
3 Vendor ID bit 3
2 Vendor ID bit 2
1 Vendor ID bit 1
0 Vendor ID bit 0
Type
R
R
R
R
R
R
R
R
Power Up Con-
dition
1
0
0
0
0
0
1
1
Output(s) Affected
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Notes
12-0168
5 www.pericom.com
P-0.1
02/29/12

5 Page










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