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PDF PI6C49004A Data sheet ( Hoja de datos )
| Número de pieza | PI6C49004A | |
| Descripción | Gen 2 Networking Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal such as Saronix-eCera™ SRX7278
• Twelve PCIe® Gen. 2 100MHz HCSL outputs with optional
-0.5% spread spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 56-pin TSSOP package
Description
The PI6C49004A is a clock generator device intended for PCIe®
Gen2 networking applications. The device includes twelve
100MHz differential Host Clock Signal Level (HCSL) outputs
for PCIe Gen 2, two single-ended 50MHz outputs, one single-
ended 32.256MHz output, and one selectable single-ended
33/66/133MHz output.
Using a serially programmable SMBUS interface, the PI6C49004A
incorporates spread spectrum modulation on the twelve 100MHz
HCSL PCIe Gen 2 outputs, and independent frequency margining
on the 50MHz output, 33.3333MHz and 66.6666MHz clock
outputs.
Pin Configuration
Block Diagram
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
VDD
12
SCLK
SDATA
PD_RESET
PLL, Dividers,
Buffers, and
Logic
12
100M_OUT(0-11)
2 50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
8
GND
ISET
475 Ohms
1%
VDD
IREF
NC
100M_Q11-
100M_Q11+
100M_Q10-
100M_Q10+
VDD
VDD
GND
100M_Q9-
100M_Q9+
100M_Q8-
100M_Q8+
100M_Q7-
100M_Q7+
SCLK
SDATA
GND
50M_OUT1
50M_OUT2
VDD
GND
VDD
32.256M_OUT1
GND
NC
PD_RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11-0104
1
56 GND
55 VDD
54 100M_Q0-
53 100M_Q0+
52 100M_Q1+
51 100M_Q1-
50 VDD
49 GND
48 VDD
47 100M_Q2+
46 100M_Q2-
45 100M_Q3+
44 100M_Q3-
43 100M_Q4+
42 100M_Q4-
41 100M_Q5+
40 100M_Q5-
39 VDD
38 GND
37 VDD
36 100M_Q6+
35 100M_Q6-
34 33/66/133M_OUT1
33 VDD
32 GND
31 VDD
30 X2
29 X1
PS-01
04/19/11
1 page  
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49004A is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 1 0/1
How to Write
1 bit 8 bits 1
8 bits
1 8 bits
1 8 bits 1
8 bits
1
Start
bit
Note:
1.
D2H
Ack
Register
offset
Ack
Byte Count
=N
Ack
Data Byte
0
Ack
…
Data Byte
N-1
Ack
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
1 bit
Stop bit
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit 8 bits
1 bit 8 bits
1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits
1 bit … 8 bits
1 bit
1 bit
M:
Start
bit
M: Send
"D2h"
S:
sends
Ack
M: send
starting
databyte
location:
N
S:
sends
Ack
M:
Start
bit
M:
Send
"D3h"
S:
sends
Ack
S:
sends #
of data
bytes
that
will be
sent: X
M:
sends
Ack
S:
sends
start-
ing
data
byte
N
M:
sends
Ack
…
S:
sends
data
byte
N+X-1
M: Not
Ac-
knowl-
edge
M:
Stop
bit
Byte 0: Spread Spectrum Control Register
Bit Description
Type
7
Spread Spectrum Selection for 100MHz HCSL PCI-
Express clocks
RW
6
Enables hardware or software control of OE bits (see
Byte 0–Bit 6 and Bit 5 Functionality table)
RW
Software PD_RESET bit. Enables or disables all out-
5 puts
RW
(see Byte 0–Bit 6 and Bit 5 Functionality table)
4 Frequency margining select bit FS3
RW
3 Frequency margining select bit FS2
2 Frequency margining select bit FS1
RW
RW
1 Frequency margining select bit FS0
RW
0 OE for single-ended 50MHz output 50M_Out2
RW
Power Up
Condition
0
Output(s)
Affected
All 100MHz HCSL
PCI Express outputs
0 PD_RESET pin, bit 5
Notes
0=spread off
1 = -0.5% down spread
0 = hardware cntl
1 = software ctrl
1
All outputs
0 = disabled
1 = enabled
1
0
1
50M_Out1 and 50M_
Out2
See 50MHz Frequency
Margining Table on
Page 3
0
1
Single-ended 50MHz
output 50M_Out2
0 = disabled
1 = enabled
11-0104
5
PS-01
04/19/11
5 Page 
PI6C49004A
PCIe® Gen 2 Networking Clock Generator
Notes:
1. Measured at the end of an 8-inch trace with a 5pF load.
2. Measurement taken from a single-ended waveform.
3. Measurement taken from a differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time.
The 300 mV measurement window is centered on the differential zero crossing.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement.
7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance,
and spread spectrum modulation.
8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–.
9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations.
10. 10) PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM
there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or
greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in
maximum period resulting from the -0.5% down spread.
Crystal Load Capacitors
If an input crystal is used, crystal should be connected from pins X1 to ground and X2 to ground to optimize the accuracy of the
output frequency.
CL = Crystal's load capacitance in pF
Crystal Capacitors (pF) = (CL - 8) *2
For example, for a crystal with a 18pF load cap, each external crystal cap would be 18pF. (18 - 8) *2 =18.
Application Notes
Crystal circuit connection
The following diagram shows PI6LC4830-01 crystal circuit connection with a parallel crystal. For the
CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the
target ppm of crystal oscillator according to different board layouts.
Crystal Oscillator Circuit
SaRonix-eCera
CG2500003
C1
27pF
Crystal�(CL�=�18pF)
C2
33pF
XTAL_IN
XTAL_OUT
11-0104
11
PS-01
04/19/11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI6C49004A.PDF ] | |
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