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PDF AND8460 Data sheet ( Hoja de datos )
| Número de pieza | AND8460 | |
| Descripción | Implementing a 12V / 240W Power Supply | |
| Fabricantes | ON Semiconductor | |
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AND8460/D
Implementing a 12 V /
240 W Power Supply with
the NCP4303B, NCP1605
and NCP1397B
Prepared by: Roman Stuler, Jaromir Uherek and Ivan Seifert
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Overview
The following document describes a 12 V / 20 A output
switch mode power supply (SMPS) intended for use as an
ATX power supply main converter or as an All−In−One PC
power supply. The reference design circuit consists of a
double sided 135 x 200 mm printed circuit board with a
height of only 35 mm. An overview of the entire SMPS
architecture is provided in Figure 1. Careful consideration
was given to optimizing performance while minimizing the
total solution cost.
EMI
Filter
90V – 265Vac
NCP1605
PFC
Controller
Frequency Clamped
Critical Conduction Mode
Power Factor Controller
NCP1397B
Resonant Controller
with built−in
Half Bridge Driver
Resonant Technology
for Increased
Efficiency and Lower EMI
Bias
circuitry
NCP4303B
SR controller
Synchronous Rectification
for improved efficiency
12V / 20A
NCP4303B
SR controller
TL431
Figure 1. Demoboard Block Diagram
Architecture Overview
The circuit utilizes the NCP1605 for an active power
factor correction front end. This stage provides a well
regulated PFC output voltage that allows optimization of the
downstream converter. The NCP1605 controller operates
using a Frequency Clamped Critical conduction Mode
control technique. The SMPS stage uses a Half Bridge
Resonant LLC topology since it improves efficiency,
reduces EMI signature and provides better transformer
utilization compared to conventional topologies. The
NCP1397B controller is used to control the Half Bridge
Resonant LLC converter. To maximize efficiency of the
LLC power stage, Synchronous Rectification (SR) has been
implemented on the secondary side. The NCP4303B SR
controller is used to achieve accurate turn−on and turn−off
of the SR MOSFETs.
In summary, the architecture selected for this reference
design allows system optimization so that the maximum
efficiency is achieved without significantly increasing the
component cost and circuit complexity.
Demoboard Specification
Most of today’s computing applications like ATX PC,
game consoles and All−in−one PC use 12 V as the main
power rail. This voltage is then further decreased to 5 V and
3.3 V by DC/DC step down converters. Because nearly all
power passes through the 12 V output, it is critical that the
efficiency of the main power stage be optimized. Most
designs today utilize an LLC topology for the power stage
to provide high efficiency at a reasonable cost. The LLC
power stage provides inherently high efficiency results
thanks to zero voltage switching (ZVS) on the primary side
and zero current switching (ZCS) on the secondary side.
Efficiency however decreases for higher output currents as
the secondary RMS current reaches a high level. The
solution for these losses on the secondary side is to use
synchronous rectification instead of conventional rectifiers
(Schottky diode). Consideration was also give to optimizing
light and no load efficiency, which is particularly important
in All−in−one PC SMPS that usually do not utilize an
additional standby power supply.
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 2
1
Publication Order Number:
AND8460/D
1 page  
AND8460/D
flowing through inductor L7 and switch Q4 is higher than the
maximum current limit level, the CS pin current increases
above the OPC threshold (250 uA) and the driver is turned
off. The CS input is also used to detect coil demagnetization
for zero current detection. The zero current detection
prevents the MOSFET from turning on when current flows
through the coil. As long as there is no coil current, the
NCP1605 operates at a frequency determined by the internal
oscillator and external capacitor C38. Zero current detection
circuitry sensitivity is adjusted by resistor R70 and R81.
To protect the PFC from sudden drops in the line voltage,
the controller monitors the rectified line voltage via
brownout divider R15, R23, R31, R50, R71 and C39.
The driver output is connected to MOSFET Q4 via
resistors R25, R26 and diode D7 to regulate turn−on speed.
Transistor Q7 is used to speed up the MOSFET turn−off time
and thus reduce turn−off losses.
Please refer to the application note AND8281/D for
detailed information on the PFC stage design and operation.
Figure 4. The LLC Stage Primary Side Connection
LLC Power Stage Primary Side
Primary Side Power Loop Connection
The PFC stage prepares a regulated voltage on bulk
capacitors C16 and C17 for the downstream LLC stage (refer
to Figure 3). The LLC stage power loop is closed through Q3
and Q5, transformer TR1 and resonant capacitors C7, C18
(Figure 4). The NCP1397 LLC controller features a 600 V
high−side driver and is capable of driving the HB power
stage directly without the use of a driver transformer.
Resistors R54 and R55 are used to suppress ringing and
control EMI noise on the power MOSFET gates. Bootstrap
capacitor C53 provides the energy required for controlling
the high side MOSFET. When Q5 is turned−on, the HB pin
voltage drops and bootstrap capacitor C53 is charged
through resistor R96 and high−voltage diode D23. At turn−on
and after any restart, the LLC controller turns on MOSFET
Q5 first to charge up the bootstrap capacitor.
The PFC and LLC controllers are powered from the
auxiliary winding W4 of transformer TR1. The PFC
controller charges up the VCC capacitors C3, C42 first when
the demoboard is plugged into the mains. Once the PFC
stage starts operation and the bulk voltage is within the
nominal operating range, the LLC stage is enabled. The
auxiliary winding also provides bias voltage for the X2
capacitor discharge circuitry via diode D1, resistor R1 and
capacitor C1. The X2 capacitor discharge circuitry is
described in the PFC Stage section (refer to page 3).
FB Loop and Skip Mode:
The minimum operating frequency of the LLC converter
is set by resistor R104 (refer to Figure 5). The maximum
operating frequency is set by resistor R102. The LLC stage
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5
5 Page 
AND8460/D
During light load conditions, the secondary current
oscillation can cause unwanted SR MOSFET switching. A
minimum on time of 1.1 ms is needed to prevent this
behavior. The required value of min Ton adjust resistors can
be calculated using Equation 20.
RT_on_min
+
Ton_min * 4.66 @
9.82 @ 10−11
10−8
+
(eq. 20)
+
1.1
@
10−6 * 4.66 @
9.82 @ 10−11
10−8
[
11
kW
Where:
RT_on_min −is the minimum on time adjust resistor
The minimum off time period is given by resistors R7,
R37. To prevent issues when the application operates at
minimum frequency, the minimum off time should be set to
as long as possible. However, the minimum off time value
is limited by the maximum operating frequency clamp. In
our case, the minimum switching period of the LLC stage is
9.1 ms. Thus the minimum off time period is selected to be
3.9 ms in order to provide a long minimum off time with
some margin for the minimum switching period. The
minimum off time adjust resistor value can by calculated
using Equation 21.
RT_off_min
+
Toff_min *
9.56 @
5.4 @ 10−8
10−11
+
+
3.9
@
10−6 * 5.4 @
9.56 @ 10−11
10−8
[
39
kW
(eq. 21)
Where:
Rt_off_min −is the minimum off time adjust resistor
If the LLC converter uses a very wide operating frequency
range, it is beneficial to modulate the minimum off time
period. The modulation is possible using a resistor
connected from the SR MOSFET drain to the opposite SR
controller min Toff pin. When the drain voltage is at a high
level, current is injected into the min Toff pin. The internal
capacitance charging current is thus decreased and the
minimum off time period increases. Please refer to the
NCP4303 datasheet for more information on how to
modulate the minimum off time period.
The NCP4303 features a trigger input that can be used to
implement synchronous rectification systems in CCM
applications. Additionally, the trigger input can be used to
disable the IC and activate a low consumption standby
mode. The demoboard layout features optional circuitry
(refer to complete schematic − page 31) that allows the
customer to implement a primary triggering signal.
Normally this is not need in LLC applications as the
NCP4303 features a low propagation delay from the CS
input to the DRV output. The trigger circuitry option is
implemented to allow the customer to test the trigger input
functionality.
The no load consumption of the application can be
reduced by implementing parallel Schottky diodes across
the SR MOSFETs and turning the SR system into sleep
mode during light load. The demoboard provides a control
input that can be used for this purpose. The external SR
standby on/off circuitry can be implemented by monitoring
output current.
It is critical to assure correct layout of the SR system to
avoid issues with the zero current detection circuitry. Please
refer to the NCP4303 datasheet for layout considerations
and more information on how the ZCD and the
compensation systems work.
The secondary filtering capacitor bank RMS current
during full load series resonant frequency operation can be
calculated using Equation 22.
ǸICf_RMS + Iout_nom @
p2
8
*
1
+
20
@
0.483
+
9.7
A
(eq.
22)
Where:
Iout_nom – is the nominal output current
Filtering capacitors must be used in parallel to handle the
total RMS current. Low impedance type capacitors have
been used in this design. The total equivalent series
resistance (ESR) of the capacitor bank is 2.25 mW. The
output voltage ripple related to the filtering capacitor bank
is composed from two components:
1st the ESR related ripple (Equation 23) and
2nd the ripple related to the capacitor bank capacitance
(Equation 24).
VCf_ripple_pk*pk + ESR @ Irect_peak + 2.2 @ 10−3 @
@
p
2
@
20
+
69
mV
(eq. 23)
Where:
Irect_peak – is the peak current through the secondary
Vout_ripple_cap_pk*pk
+
2
@
Ǹ3
Iout_nom
@ p @ fop_nom
@
Cf
@
(eq. 24)
@ ǒ p * 2Ǔ + 20 @ ǒ p * 2Ǔ + 10 mV
2 @ Ǹ3 @ 80 @ 103 @ 8 @ 10−3
Where:
fop_nom – is the nominal operating frequency
Cf – is the total capacitance of the capacitor bank
The capacitive component of the output ripple is
negligible in this case because of the total filtering
capacitance value.
The power losses that are created by the filtering capacitor
bank ESR can be calculated using Equation 25.
ǒ Ǹ ǓPCf_ESR + Iout_nom @
p2
8
*
1
2
@ ESR +
(eq. 25)
ǒ Ǹ Ǔ+ 20 @
p2
8
*
1
2
@ 2.25 @ 10−3 + 0.21 mW
The PCB secondary side layout can significantly affect
current distribution among the filtering capacitors. Ideally,
the secondary layout should result in an equal distribution of
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| PDF Descargar | [ Datasheet AND8460.PDF ] | |
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