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PDF HV507PG-G Data sheet ( Hoja de datos )
| Número de pieza | HV507PG-G | |
| Descripción | 64-Channel Serial to Parallel Converter | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Supertex inc.
HV507
64-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
► Processed with HVCMOS® technology
► Operating output voltages to 300V
► Low power level shifting from 5.0 to 300V
► Shift register speed: 8.0MHz @ VDD = 5.0V
► 64 latched data outputs
► Output polarity and blanking
► CMOS compatible inputs
► Forward and reverse shifting options
General Description
The HV507 is a low voltage serial to high voltage parallel
converter with 64 push-pull outputs. This device has been
designed for use as a printer driver for electrostatic applications.
It can also be used in any application requiring multiple output,
high voltage, low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through
the device. With DIR grounded, DIOA is Data-In and DIOB is
Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR
is at logic high, DIOB is Data-In and DIOA is Data-Out: data is
then shifted from HVOUT1 to HVOUT64. Data is shifted through
the shift register on the low to high transition of the clock. Data
output buffers are provided for cascading devices. Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL(polarity) inputs. Transfer of data from the
shift register to the latch occurs when the LE is high. The data in
the latch is stored during LE transition from high to low.
Functional Block Diagram
POL
BL
Latch Enable
DIOA
CLOCK
64 bit
Static Shift
DIR Register
64
Latches
DIOB
VPP
L/T
L/T
L/T
L/T
L/T = Level Translator
HVOUT1
HVOUT2
•
•
•
60 Additional
Outputs
•
•
•
HVOUT63
HVOUT64
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page  
HV507
Function Table
Inputs
Outputs
Function
Data CLK LE BL POL DIR
Shift Reg
1 2...64
HV Outputs
1 2...64
All on X X X L L X * *...*
All off X X X L H X * *...*
Invert mode
X
X LHLX
*
*...*
Load S/R H or L ↑
L H H X H or L *...*
Store data in
X
X ↓ HHX
*
*...*
latches
X X ↓HLX
*
*...*
Transparent
L
↑ HHHX
L
*...*
latch mode
H
↑ HHHX
H
*...*
I/O Relation
DIOA
DIOB
↑
↑
XXX L
XXXH
Qn→
Qn→
Qn+1
Qn+1
Notes:
H = high level, L = low level , X = irrelevant, ↑ = low-to-high transition ↓ = high-to-low transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.
H H...H
L L...L
* *...*
* *...*
* *...*
* *...*
L *...*
H *...*
-
-
Data Out
*
*
*
*
*
*
*
*
*
DIOB
DIOA
Pin Description (80-Lead PQFP)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function
HVOUT41
HVOUT42
HVOUT43
HVOUT44
HVOUT45
HVOUT46
HVOUT47
HVOUT48
HVOUT49
HVOUT50
HVOUT51
HVOUT52
HVOUT53
HVOUT54
HVOUT55
HVOUT56
HVOUT57
HVOUT58
HVOUT59
HVOUT60
Pin #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Function
HVOUT61
HVOUT62
HVOUT63
HVOUT64
VPP
DIOA
N/C
N/C
BL
POL
VDD
DIR
GND
HVGND
N/C
N/C
CLK
LE
DIOB
VPP
Pin #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Function
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
Pin #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Function
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
HVOUT33
HVOUT34
HVOUT35
HVOUT36
HVOUT37
HVOUT38
HVOUT39
HVOUT40
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
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| PDF Descargar | [ Datasheet HV507PG-G.PDF ] | |
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