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PDF HV461 Data sheet ( Hoja de datos )
| Número de pieza | HV461 | |
| Descripción | Ring Generator Controller IC | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Supertex inc.
HV461
Ring Generator Controller IC
Features
►► 3.3V operation, logic inputs 3.3V & 5.0V compatible
►► Digital control of ring frequency, amplitude, and offset
►► Control via 8-bit bus or via individual inputs
►►
8 built-in ring
50, 60Hz
frequencies:
12,
162/3,
20,
25,
331/3,
40,
►► External ring frequency input
►► Low distortion sine wave synthesizer
►► AC-only, AC+DC, or DC-only ringer output
►► Adjustable over-current protection
►► Internal precision voltage references
►► Power-on reset and undervoltage lockout for hotswap
capability
►► Sync output with adjustable lead time for synchronizing
ringing relays
►► Fault output for problem detection
►► Open or closed loop operation
►► Efficient 4-quadrant operation
►► Zero-cross turn-on with zero-cross turn-off option
Applications
►► PBX
►► DLC
►► Key Systems
►► Remote Terminal
►► Wireless Loop Systems
General Description
The HV461FG is a highly integrated ring generator controller
IC, designed to work with a patented four-quadrant inverter
topology, with synchronous rectifiers on the secondary side to
achieve higher efficiencies. The inverter delivers the desired
ring voltage from a standard -48V Telecom power supply.
The HV461 consists of a sine wave synthesizer that can provide
eight different ring frequencies for universal applications. Any
other frequency in the 12 to 63Hz range can be obtained by
applying an external logic signal to the IC. A transparent latch
permits control of the ringer output individually or through the
8-bit bus. The output amplitude and DC offset can be digitally
controlled providing high flexibility to the designers. The
patented inverter topology using the HV461 controller IC is
capable of achieving higher efficiencies, typically over 80%,
and drive up to a 40 REN load.
The controller allows ring generators to provide a floating
94VAC (rms) waveform that can be referenced to either the
-48V or any other offset level by using the programmable
offset pins of the IC. Output offset may be achieved by directly
generating the offset within the power stage, or by floating the
output stage on a DC source, or both.
The HV461 also has an internal boost converter that can be
used to provide the gate drive voltages for the two MOSFETS
on the primary side and the two secondary rectifiers on the
secondary side.
Typical Application Circuit
+3.3V
I/O
-48V
Current Sense
Xtal
VDD Gate Drive
Out
HV461
-48V
0V
-48V
OR
94VAC(rms)
Doc.# DSFP - HV461
C071913
Supertex inc.
www.supertex.com
1 page  
External Ring Frequency
Sym Parameter
fCAP(lo)
Capture frequency low*
fCAP(hi)
Capture frequency high*
VIN(lo)
Input low
VIN(hi)
Input high
∆θRING Phase jitter, sine ref out
* Lock range is the same as capture range
Sine Reference Attenuator
Sym Parameter
VDC
AOFF
ALO
AMED
AHI
DC level
Attenuation
Attenuation
Attenuation
Attenuation
VIN Input range
DC REF Multiplexer
Sym Parameter
VIN Input range
IIN Input bias current
IOFF Off leakage current
Enable and SYNC
Sym Parameter
VOUT(lo)
VOUT(hi)
tON
SYNC output voltage low
SYNC output voltage high
ENABLE delay, on
tOFF ENABLE delay, off
τSYNC(ON) SYNC on lead time
τSYNC(OFF)
tSYNC(rise)
tSYNC(fall)
SYNC off delay
SYNC rise time
SYNC fall time
HV461
Min Typ Max Units Conditions
- 12 - Hz loop filter = (33µF+10kΩ)||4.7µF
- 63 - Hz loop filter = (33µF+10kΩ)||4.7µF
- - 0.3 - VDD V ---
0.7·VDD
-
- V ---
-5 - +5 deg loop filter = (33µF+10kΩ)||4.7µF
Min
1.213
-
0.490
0.735
0.980
0.2
Typ
1.250
-
0.500
0.750
1.000
-
Max
1.288
0.010
0.510
0.765
1.020
Units
V
V/V
V/V
V/V
V/V
Conditions
VIN(DC) = 1.250V
AMP = 00
AMP = 01
AMP = 10
AMP = 11
VDD - 0.2
V ---
Min Typ Max Units Conditions
0.0 - VDD V ---
-500
-
+500
nA ---
- - 1.0 µA VIN = 0.5 to VDD- 0.5V
Min
-
VDD - 0.2
-
Typ
-
-
-
0-
4.5
-250
-
-
5.0
0
-
-
Max
0.2
-
5
60
1
5.5
+250
300
300
Units
V
V
µs
µs
ring
cycle
ms
µs
ns
ns
Conditions
IOUT = 1.0mA sink
IOUT = 1.0mA source
---
SYNCMODE = 0
SYNCMODE = 1
CSINE = 0
RSYNC = 154kΩ
CSYNC = 47nF
CSINE = 10nF
CL = 50pF
CL = 50pF
Doc.# DSFP - HV461
C071913
Supertex inc.
5 www.supertex.com
5 Page 
HV461
Pin Description (refer to pin configuration on page 2)
Pin
Name
Description
1 DCREF3 See DCREF1 and DCREF2 (pins 47 & 48).
2 VREF1 Outputs a 1.25V nominal reference voltage. Bypass with a 100nF capacitor to ground.
3 VREF2 Outputs a 2.50V nominal reference voltage. Bypass with a 100nF capacitor to ground.
4
AVDD
Supply for the analog section. 3.0 to 3.6V Must be from the same source as DVDD. Bypass with
a 100nF capacitor to ground as close as possible to the IC.
5
TSYNC
An RC network connected to this pin determines the SYNC pulse lead time (see SYNC pin 14).
tLEAD = 0.48RC If SYNC is not utilized, TSYNC must still have a connected RC network.
A crystal from this pin to ground provides the frequency reference for the internal sine wave
6
XTAL
synthesizer. A 19.6608MHz baud rate crystal provides the 8 most common ring frequencies. The
crystal is operated in the series mode. A loading capacitor is not necessary. See also FREQ0–2
(pins 21–23) and FRING (pin 7).
Ring frequency is normally selected from the 8 built-in frequencies using control inputs FREQ0–
2. Other arbitrary frequencies in the range of 12 to 63Hz may be obtained by applying an external
signal to FRING. This external signal sets the ring frequency at a 1:1 ratio. The ring signal
7 FRING remains a sine wave, with amplitude and offset still controlled via AMPx and OFFx. The ring
signal, while frequency locked to the FRING signal, is not phase–synchronized to it. This allows
the ring signal to immediately start at 0º when enabled via ENABLE or AMP ≠ 00. When unused,
this input must be connected to VGD.
Phase locked loop filter. An RC network connected to this pin stabilizes the PLL that locks on to
the optional external ring frequency signal. (See FRING, pin 7) The RC network determines the
8 PLLFLT lock time of the PLL. Due to the low frequencies involved, it may take a couple seconds to lock
to the external signal. See the typical application schematic for typical values. When unused, this
pin should be left unconnected.
9
ROSC
A resistor from this pin to VDD sets the PWM frequency. fPWM ≈ 12.5GHzΩ / ROSC (valid for 20-
150kHz)
A capacitor from this pin to ground provides a power–on reset interval. It has an internal 10µA
pull–up to charge the external reset capacitor. Alternatively, an external logic–level or open–
10
RESET
drain signal may be applied to implement the reset function. During the reset interval when
VRESET<1.325V, the ringer output is disabled regardless of the state of the ENABLE input, allowing
time for the host controller to assume control. Use a low leakage tantalum or ceramic capacitor.
tRESET = 1.325V · CRESET / 10µA
This pin functions as both an input and an output. It is open–drain with an internal 100µA pull-
up. As an output, it provides a short, low-going pulse at the internal PWM frequency. As an
input, it synchronizes internal PWM frequency to the externally applied signal, provided the
11
PWMSYNC
external signal is at a higher frequency. The low-going applied sync pulse should be between
25ns and less than the PWM period in duration. The external source should be open drain. If
the PWMSYNC pins of multiple HV461s are tied together, their PWM frequencies will be phase-
locked to the HV461 with the highest free-running frequency. A maximum of 10 HV461s may be
tied together. If unused, this pin should be left unconnected.
A capacitor from this pin to ground sets the integration time of the FAULT detection circuitry.
12
CFAULT
A larger capacitor provides less suseptability to transient problems, while a smaller capacitor
provides quicker response. Values in the range of 1µF to 100µF are appropriate. If the FAULT
output is not used, this pin should be grounded. See also FAULT (pin 15).
Doc.# DSFP - HV461
C071913
Supertex inc.
11 www.supertex.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HV461.PDF ] | |
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