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PDF HV311LG-G Data sheet ( Hoja de datos )
| Número de pieza | HV311LG-G | |
| Descripción | Hot Swap Controller | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HV311LG-G (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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HV311
Hot Swap Controller
Features
► 10 to 90V operation, positive or negative
supply
► UV/OV lock out & power-on-reset
► Circuit breaker
► 100ms startup timer
► Automatic retry or latched operation
► Low Power, 400µA sleep mode
► Active low power good
► 8-Lead SOIC package
General Description
The Supertex HV311 Hot Swap Controller provides inrush current limiting and
other power supply support functions for hot swap equipment. Current limiting is
provided by control of an external MOSFET which is placed in the return line of
the power supply connection. Placement in the return allows use of an N-channel
MOSFET without the need for high side driving.
An internal clamp at the GATE pin activates when full bias for the HV311 is not
available, thus keeping the MOSFET in the off-state during the initial insertion
phase. As soon as adequate bias is available for the main control circuits, the UV
(undervoltage) and OV (overvoltage) pins check for normal operating voltage on
the power supply input.
Applications
► 48V central office switching
► 24V cellular and fixed wireless systems
► 24V PBX systems
► Line cards
► 48V powered ethernet for VoIP
► Distributed power systems
► Power supply control
► 48V storage networks
► Electronic circuit breaker
Once normal operating voltage is present, the GATE voltage for the external
MOSFET ramps up at a constant rate. The rate is controlled by the value of an
external capacitor placed at the RAMP pin. At some point the external MOSFET
channel is enhanced, allowing power supply current to flow, thereby energizing
downstream power supply capacitors.
During the GATE ramp up the power supply current is monitored with the aid
of an external sense resistor which forces reduction in the ramp rate when the
power supply current reaches a set limit. The limit is set by the value of the
external sense resistor and the threshold of the current sense amplifier (50mV).
Once inrush current subsides, the GATE voltage resumes its rise to the output
voltage of an internal regulator VREG, with an output voltage ranging from 8.5
to 12V. When GATE is within 1.2V of VREG, GATE is pulled high to VREG with an
internal switch, the open-drain PWRGD pin pulls low, and the HV311 enters a
low power mode.
Typical Application Circuit
The HV311 includes a start-up timer and a circuit breaker function to protect
the MOSFET from excessive power dissipation. The start-up timer trips when
the start-up phase exceeds 100ms. The circuit breaker trips at double the
current limit threshold (100mV). Upon tripping of either the start-up timer or
the circuit breaker the MOSFET is turned off, and the PWRGD pin becomes
high impedance. Thereafter, a programmable automatic retry timer allows the
MOSFET to cool down before resetting and restarting. The automatic retry can
be disabled by adding an external resistor at the RAMP pin (about 2.5MΩ, see
applications section).
GND
8
R1
487kΩ
R2
6.81kΩ
VDD
3 UV
2 OV
PWRGD 1
HV311
ENABLE
CLOAD
DC/DC
PWM
CONVERTER
+5.0V
COM
R3
9.76kΩ
-48V
VEE
4
SENSE
5
R4
12.5mΩ
GATE RAMP
6 7 C1
10nF
-48V
Q1
IRF530
NOTES:
1. Undervoltage threshold (UV) set to 35V.
2. Overvoltage threshold (OV) set to 65V.
3. Startup current set to 4A.
4. Circuit breaker set to 8A.
5. 100ms max startup time.
6. Automatic retry enabled.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page  
HV311
Functional Description (cont.)
Once external power supply capacitors are charged, the
power supply current subsides, and the RAMP current in-
creases again to its maximum value of 10μA. The RAMP
and GATE voltages resume their rise. When the RAMP volt-
age is within 1.2V of the internal supply, then GATE is con-
nected to the internal supply, and the open-drain PWRGD
pin is pulled low, marking the end of the start-up.
If the start-up sequence is not finished within 100ms, then
the internal start-up timer causes a reset of the RAMP and
GATE voltage to 0V, and the automatic retry timer is started
to allow the MOSFET to cool off. After the retry delay a new
startup sequence is initiated if the power supply voltage is
within the normal operating range, as determined by the UV
and OV comparators.
The circuit breaker monitors the sense amplifier for the pres-
ence of an overcurrent condition at all times. The overcur-
rent threshold is set at twice the maximum inrush current
threshold. Should overcurrent occur, then RAMP and GATE
are brought to zero, PWRGD returs to high impedance, and
the automatic retry timer is started.
The automatic retry timer can be disabled by attachment of
an additional resistor at the RAMP pin if a latched shutdown
is desired.
A further reduction in the ramp rate of the RAMP and GATE
voltages can be attained by connection of a feedback ca-
pacitor from the drain node to the RAMP pin. During startup
the drain voltage drops at a rate proportional to the inrush
current. This falling voltage waveform can be used to fur-
ther reduce the current that flows onto the RAMP capacitor,
thereby reducing the maximum inrush current.
Design Information
Setting up the UV and OV comparators
The following example shows how the resistors for the
threshold setting divider can be determined. The procedure
applies to the (R1, R2, R3) divider having two taps as shown
on the typical applications diagram.
The following procedure bases the selection of the divider
resistors on specification of the shutdown / disable voltages.
A similar procedure can be devised that bases selection on
specification of the enable voltages.
R2 follows from the UV shutdown voltage:
• DFUV = (R2 + R3) / R123
• VFTH = VUVS · DFUV
• R2 + R3 = R123 · VFTH / VUVS
• R2 = 6.879kΩ (6.81k 1%)
And:
• R1 = 483.429kΩ (487k 1%)
Let’s assume the following:
• nominal divider current draw INOM = 100μA,
• nominal power supply voltage VNOM = 50V,
• overvoltage shutdown voltage VOVS = 65V,
• undervoltage shutdown voltage VUVS = 35V,
• negligible (UV, OV) comparator input currents,
• Comparator rising threshold VRTH = 1.26V
• Comparator falling threshold VFTH = 1.16V
Now the upper and lower enable voltages can be deter-
mined:
• Lower Enable Voltage VLEN
• Upper Enable Voltage VUEN
• VRTH = DFUV · VLEN
• VFTH = DFOV · VUEN
• VLEN = 38.0V
• VUEN = 59.8V
The following applies:
• R123 = (R1 + R2 + R3)
• R123 = VNOM / INOM
• R123 = 500kΩ
R3 follows from the OV shutdown voltage:
• DFOV = R3 / R123
• VRTH = VOVS · DFOV
• R3 = R123 · VRTH / VOVS
• R3 = 9.692kΩ (97.6k 1%)
Programming Maximum Inrush Current and Circuit
Breaker Current
The values of the current limit threshold voltage VCL and the
external current sense resistor RCS determine the maximum
power supply current during startup IMAX (the maximum in-
rush current). Similarly the circuit breaker trip current ICB is
determined by the values of the circuit breaker threshold
voltage VCB and the value of RCS.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
5 Page 
HV311
Application Circuit 7
Using Short Connector Pin
In some systems short connector pins are used to guarantee that the power pins are fully mated before the hot swap control
circuit is enabled. For these systems the positive (VDD) end of the R1, R2, and R3 resistor divider should be connected to
Long
Pin
GND Short
Pin
GND R1
487kΩ
R2
6.81kΩ
8
VDD
3 UV
2 OV
PWRGD 1
HV311
ENABLE
CLOAD
DC/DC
PWM
CONVERTER
-48V
R3
9.76kΩ
Long
Pin
RAMP
7
C1
10nF
VEE
4
SENSE GATE
56
R4
12.5mΩ
Q1
IRF530
Note:
A capacitor may be needed to slow PWRGD dv/dt if gate oscillations are observed when VIN is close to OVLO.
+5.0V
COM
Application Circuit 8
If separate resistor dividers are used for OV and UV, then only the positive (VDD) end of the UV resistor divider should be
connected to the short pin.
Long
Pin
GND
Short
Pin
GND R1
475KΩ
R2
16.2KΩ
-48V
Long
Pin
R3
511KΩ
8
VDD
3 UV
PWRGD 1
HV311
2 OV
R4 RAMP
10KΩ
7
C1
10nF
VEE
4
SENSE GATE
56
ENABLE
CLOAD
DC/DC
PWM
CONVERTER
R5
12.5mΩ
Q1
IRF530
Note:
A capacitor may be needed to slow PWRGD dv/dt if gate oscillations are observed when VIN is close to OVLO.
+5.0V
COM
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HV311LG-G.PDF ] | |
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