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UJA1061TW の電気的特性と機能

UJA1061TWのメーカーはPhilipsです、この部品の機能は「Low speed CAN/LIN system basis chip」です。


製品の詳細 ( Datasheet PDF )

部品番号 UJA1061TW
部品説明 Low speed CAN/LIN system basis chip
メーカ Philips
ロゴ Philips ロゴ 




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UJA1061TW Datasheet, UJA1061TW PDF,ピン配置, 機能
www.DataSheet4U.com
INTEGRATED CIRCUITS
DATA SHEET
UJA1061
Low speed CAN/LIN system
basis chip
Objective specification
2004 Mar 22

1 Page





UJA1061TW pdf, ピン配列
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
1 FEATURES
1.1 General
Excellent EMC performance
• ± 8 kV ESD protection (human body model) for the
outside module pins
CAN/LIN-bus pins are short-circuit proof to the battery
(up to 60 V) and to ground
Battery and CAN/LIN-bus pins are protected against
transients that occur in an automotive environment
(ISO7637)
Software Development mode partly disabling of fail-safe
and watchdog functionality to ease software
development
Unique SPI readable device type identification
Small footprint HTSSOP32 package (body 6 × 11 mm)
with low thermal resistance.
1.2 System features
12 V, 24 V and 42 V system support with low sleep
current (typical 50 µA)
Support of 2.5, 3.0, 3.3 and 5.0 V microcontrollers with
automatic adaption of interface levels to
microcontrollers
Flexible, independent external regulator extension via
14 V battery related pin INH (enables fail-safe scalable
supply system)
Smart operating and power management modes
In-field Flash Programming mode
Cyclic wake-up capability in Standby and Sleep mode
Remote wake-up capability via CAN and LIN buses
Local WAKE port with cyclic supply feature
42 V battery related local wake-up input
42 V battery related high-side switch output to drive
external loads such as relays and wake-up switches
Interrupt output with 12 maskable interrupt sources:
– Interrupt service monitor
– One interrupt per watchdog period to prevent
microcontroller overloading; ensures predictable
software behaviour
Extensive set of SPI-readable system diagnostics:
– Detection and detailed error reporting on CAN and
LIN bus failures (e.g. shorts to GND/BAT, open bus
wires, etc.)
– TxD dominant and RxD recessive clamping as well
as RxD to TxD short detection to prevent bus
deadlocks
– Local ECU ground-shift detection with two selectable
thresholds
– Over-temperature warning
– Battery monitoring to detect battery interrupt or a
chattering battery contact to store data before
microcontroller power down (e.g. to store seat
position)
– Signalling of potential RAM-retention errors due to
low microcontroller VCC.
1.3 Fail-safe features
Programmable fail-safe coded window and time-out
watchdog with on-chip oscillator, guaranteeing
autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface to microcontroller,
including chip-select pin for multiple SPI devices on the
same bus
Integrated fail-safe and system features:
– Rigorous error handling based on diagnostics
– 12 dedicated reset sources supporting different,
history dependent, software start-up and diagnosis
– Global enable pin for control of safety critical
hardware
– Limp home output signal for activating application
hardware in case system enters Fail-safe mode
(e.g. switch on parking lights)
– Single SPI message; no assembly of multiple SPI
frames
– Programmable active-low system reset with
detection of both clamped and open reset line to
prevent system deadlocks
– Fail-safe coded activation of Software Development
mode and Flash mode
– 24-bit access-protected RAM can be used, for
instance, for logging of cyclic problems.
2004 Mar 22
3


3Pages


UJA1061TW 電子部品, 半導体
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
5 PINNING
SYMBOL
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
INH/LIMP
WAKE
RTL
V2
CANH
CANL
GND
RTH
LIN
RTLIN
BAT14
n.c.
2004 Mar 22
PIN DESCRIPTION
1 not connected
2 not connected
3 transmit data input to activate the LIN output drive; LOW = LIN-bus dominant;
HIGH = LIN-bus recessive
4 regulated supply voltage output for microcontroller; voltage is 5 V, 3.3 V, 3 V
or 2.5 V according to version
5 receive data output for reading data from the LIN-bus; LOW when LIN-bus is
dominant; HIGH when LIN-bus is recessive
6 active LOW push-pull output used to reset the microcontroller; the UJA1061 also
monitors the voltage on pin RSTN for any clamping situation (fail-safe)
7 active LOW open-drain output used to interrupt the microcontroller; pin INTN is to
be wire-ANDed with other interrupt outputs within the ECU
8 push-pull enable output related to voltage regulator V1; active HIGH if the watchdog
is triggered successfully and a control bit is set; immediately pulled LOW with any
reset event (e.g. a watchdog overflow); full set/clear application access via SPI
while watchdog is served properly
9 SPI data input
10 SPI data output
11 SPI clock input
12 active LOW select input used to enable an SPI access
13 transmit data input that activates the CAN output driver; LOW = CAN-bus dominant;
HIGH = CAN-bus recessive
14 receive data output for reading data from the CAN-bus; LOW when CAN-bus is
dominant; HIGH when CAN-bus is recessive; output is continuously LOW upon a
wake-up event received via the CAN-bus
15 not connected
16 test pin; connect to ground in application
17 14 V battery related inhibit output for system extension, or ‘limp home’ output,
activated in Fail-safe mode (default floating)
18 42 V battery related local wake-up input
19 CAN termination resistor connection; in case of a CANL bus wire error this line is
terminated with a selectable impedance
20 regulated 5 V supply output reserved for CAN transceiver; an external buffer
capacitor connects to this pin
21 CAN-bus line; HIGH in dominant state and LOW in recessive state
22 CAN-bus line; LOW in dominant state and HIGH in recessive state
23 ground
24 CAN termination resistor connection; in case of a CANH bus wire error this line is
terminated with a selectable impedance
25 LIN-bus line; LOW when LIN-bus is dominant, HIGH when LIN-bus is recessive
26 LIN-bus termination resistor connection
27 14 V battery supply input
28 not connected
6

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共有リンク

Link :


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Low speed CAN/LIN system basis chip

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