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PDF 34AA04 Data sheet ( Hoja de datos )
| Número de pieza | 34AA04 | |
| Descripción | EEPROM | |
| Fabricantes | Microchip | |
| Logotipo |  |
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34AA04
4K I2C™ Serial EEPROM with Software Write-Protect
Device Selection Table
Part
Number
VCC Max. Clock Temp
Range Frequency Ranges
34AA04
1.7-3.6
1 MHz(1)
I, E
Note 1: 400 kHz for 1.8V ≤ VCC < 2.2V
100 kHz for VCC < 1.8V
Features
• 4 Kbit EEPROM:
- Internally organized as two 256 x 8-bit banks
- Byte or page writes (up to 16 bytes)
- Byte or sequential reads within a single bank
- Self-timed write cycle (5 ms max.)
• JEDEC® JC42.4 (EE1004-v) Serial Presence
Detect (SPD) Compliant for DRAM (DDR4)
modules
• High-Speed I2C™ Interface:
- Industry standard 1 MHz, 400 kHz, and
100 kHz
- Schmitt Trigger inputs for noise suppression
- SMBus-compatible bus time out
- Cascadable up to eight devices
• Write Protection:
- Reversible software write protection for four
individual 128-byte blocks
• Low-Power CMOS Technology:
- Voltage range: 1.7V to 3.6V
- Write current: 1.5 mA at 3.6V
- Read current: 200 µA at 3.6V, 400 kHz
- Standby current: 1 µA at 3.6V
• High Reliability:
- More than one million erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-lead PDIP, SOIC, TSSOP, TDFN, and UDFN
Packages
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description
The Microchip Technology Inc. 34AA04 is a 4 Kbit
Electrically Erasable PROM which utilizes the I2C serial
interface and is capable of operation across a broad
voltage range (1.7V to 3.6V). This device is JEDEC
JC42.4 (EE1004-v) Serial Presence Detect (SPD)
compliant and includes reversible software write
protection for each of four independent 128 x 8-bit
blocks. The device features a page write capability of
up to 16 bytes of data. Address pins allow up to eight
devices on the same bus.
The 34AA04 is available in the 8-lead PDIP, SOIC,
TSSOP, TDFN, and UDFN packages.
Package Types
PDIP/SOIC/TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
TDFN/UDFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
Block Diagram
A0 A1 A2
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
HV Generator
Block 0
(000h-07Fh)
Block 1
(080h-0FFh)
Block 2
(100h-17Fh)
Block 3
(180h-1FFh)
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
2014 Microchip Technology Inc.
DS20005271B-page 1
1 page  
34AA04
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Symbol PDIP
SOIC
TSSOP UDFN
TDFN
Description
A0/VHV
A1
1
2
1
2
1 1 1 Chip Address Input, High-Voltage Input
2 2 2 Chip Address Input
A2 3
3
3
3 3 Chip Address Input
VSS
SDA
4
5
4
5
4 4 4 Ground
5 5 5 Serial Address/Data I/O
SCL 6
6
6
6 6 Serial Clock
NC
VCC
Note:
7 7 7 7 7 Not Connected
8 8 8 8 8 +1.7V to 3.6V Power Supply
Exposed pad on TDFN/UDFN can be connected to VSS or left floating.
2.1 A0, A1, A2 Chip Address Inputs
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 34AA04 devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either VSS or
VCC.
The A0 pin also serves as the high-voltage input for
enabling the SWPn and CWP instructions.
Note:
The comparison between the A0, A1, and
A2 pins and the corresponding Chip
Select bits is disabled for software Write-
Protect and Bank Select commands.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.2 Serial Address/Data Input/Output
(SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2014 Microchip Technology Inc.
DS20005271B-page 5
5 Page 
34AA04
FIGURE 6-2:
Bus Activity
Master
SDA Line
Bus Activity
PAGE WRITE
S
T
A
R
Control
Byte
T
S
Array
Address (n)
AA
CC
KK
Data (n)
Data (n + 1)
Data (n + 15)
S
T
O
P
P
AAA
CCC
KKK
2014 Microchip Technology Inc.
DS20005271B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 34AA04.PDF ] | |
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