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25AA02E64 の電気的特性と機能

25AA02E64のメーカーはMicrochipです、この部品の機能は「EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 25AA02E64
部品説明 EEPROM
メーカ Microchip
ロゴ Microchip ロゴ 




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25AA02E64 Datasheet, 25AA02E64 PDF,ピン配置, 機能
25AA02E48/25AA02E64
2K SPI Bus Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity
Device Selection Table
Part Number
25AA02E48
25AA02E64
VCC Range
1.8V-5.5V
1.8V-5.5V
Page Size
16 Bytes
16 Bytes
Features
• Pre-Programmed Globally Unique, 48-bit or 64-bit
Node Address
• Compatible with EUI-48™ and EUI-64™
• 10 MHz Maximum Clock Frequency
• Low-Power CMOS Technology:
- Maximum Write Current: 5 mA at 5.5V
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 µA at 2.5V
• 256 x 8-bit Organization
• Write Page Mode (up to 16 bytes)
• Sequential Read
• Self-Timed Erase and Write Cycles
(5 ms maximum)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• Temperature Ranges Supported:
- Industrial (I): -40C to +85C
• Pb-Free and RoHS Compliant
Package Types (not to scale)
6-Lead SOT-23
(OT)
SOIC
(SN)
SCK 1
VSS 2
SI 3
6 VDD
5 CS
4 SO
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
Temp. Ranges
I
I
Packages
SN, OT
SN, OT
Node Address
EUI-48™
EUI-64™
Description
The Microchip Technology Inc.
25AA02E48/25AA02E64 (25AA02EXX) is a 2 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Note:
25AA02EXX is used in this document as a
generic part number for the
25AA02E48/25AA02E64 devices.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25AA02EXX is available in the standard 8-lead
SOIC and 6-lead SOT-23 packages.
Pin Function Table
Name
Function
CS Chip Select Input
SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK
HOLD
VCC
Serial Clock Input
Hold Input
Supply Voltage
2008-2016 Microchip Technology Inc.
DS20002123F-page 1

1 Page





25AA02E64 pdf, ピン配列
25AA02E48/25AA02E64
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Test Conditions
1 FCLK Clock Frequency
— 10 MHz 4.5V VCC 5.5V
— 5 MHz 2.5V VCC 4.5V
— 3 MHz 1.8V VCC 2.5V
2 TCSS CS Setup Time
50 — ns 4.5V VCC 5.5V
100 — ns 2.5V VCC 4.5V
150 — ns 1.8V VCC 2.5V
3 TCSH CS Hold Time
100 — ns 4.5V VCC 5.5V
200 — ns 2.5V VCC 4.5V
250 — ns 1.8V VCC 2.5V
4 TCSD CS Disable Time
50 — ns
5 TSU Data Setup Time
10 — ns 4.5V VCC 5.5V
20 — ns 2.5V VCC 4.5V
30 — ns 1.8V VCC 2.5V
6 THD Data Hold Time
20 — ns 4.5V VCC 5.5V
40 — ns 2.5V VCC 4.5V
50 — ns 1.8V VCC 2.5V
7 TR CLK Rise Time
— 100 ns Note 1
8 TF CLK Fall Time
— 100 ns Note 1
9 THI Clock High Time
50 — ns 4.5V VCC 5.5V
100 — ns 2.5V VCC 4.5V
150 — ns 1.8V VCC 2.5V
10 TLO Clock Low Time
50 — ns 4.5V VCC 5.5V
100 — ns 2.5V VCC 4.5V
150 — ns 1.8V VCC 2.5V
11 TCLD Clock Delay Time
50 — ns
12 TCLE Clock Enable Time
50 — ns
13
TV Output Valid from Clock
50 ns 4.5V VCC 5.5V
Low — 100 ns 2.5V VCC 4.5V
— 160 ns 1.8V VCC 2.5V
14 THO Output Hold Time
0 — ns Note 1
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2008-2016 Microchip Technology Inc.
DS20002123F-page 3


3Pages


25AA02E64 電子部品, 半導体
25AA02E48/25AA02E64
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 25AA02EXX is a 256-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
software to match the SPI protocol.
The 25AA02EXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA02EXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25AA02EXX
followed by an 8-bit address. See Figure 2-1 for more
details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(FFh), the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 2-1).
2.3 Write Sequence
Prior to any attempt to write data to the 25AA02EXX,
the write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25AA02EXX. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
driven high, data will not be written to the array since
the write enable latch was not properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address, and then the
data to be written. Up to 16 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. Additionally, a page address begins with
XXXX 0000 and ends with XXXX 1111. If the internal
address counter reaches XXXX 1111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and
over-write any data that previously existed in those
locations.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 2-2 and Figure 2-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the write
is in progress, the STATUS register may be read to
check the status of the WIP, WEL, BP1 and BP0 bits
(Figure 2-6). Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the write cycle is completed, the write enable latch is
reset.
DS20002123F-page 6
2008-2016 Microchip Technology Inc.

6 Page



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部品番号部品説明メーカ
25AA02E64

EEPROM

Microchip
Microchip


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