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K4D261638K-LC40 の電気的特性と機能

K4D261638K-LC40のメーカーはSamsungです、この部品の機能は「128Mbit GDDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 K4D261638K-LC40
部品説明 128Mbit GDDR SDRAM
メーカ Samsung
ロゴ Samsung ロゴ 




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K4D261638K-LC40 Datasheet, K4D261638K-LC40 PDF,ピン配置, 機能
K4D261638K
128M GDDR SDRAM
128Mbit GDDR SDRAM
2M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.3
July 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 /19 -
Rev. 1.3 July 2007

1 Page





K4D261638K-LC40 pdf, ピン配列
K4D261638K
128M GDDR SDRAM
2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
1.0 FEATURES
• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 2,3(clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going
edge of the system clock
• Differential clock input
• Wrtie-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• Lead free 66pin TSOP-II (RoHS compliant)
• Maximum clock frequency up to 250MHz
• Maximum data rate up to 500Mbps/pin
2.0 ORDERING INFORMATION
Part NO.
Max Freq.
K4D261638K-LC40
250MHz
K4D261638K-LC50
200MHz
* K4D261638K-TC is the Leaded package part number.
* For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V.
Max Data Rate
500Mbps/pin
400Mbps/pin
Interface
SSTL_2
Package
66pin TSOP-II
3.0 GENERAL DESCRIPTION
FOR 2M x 16Bit x 4 Bank DDR SDRAM
The K4D261638K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fab-
ricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
mance up to 1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
- 3 /19 -
Rev. 1.3 July 2007


3Pages


K4D261638K-LC40 電子部品, 半導体
K4D261638K
6.0 BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank)
128M GDDR SDRAM
CK,CK
ADDR
Bank Select
CK, CK
16
Intput Buffer
Data Input Register
Serial to parallel
LWE
LDMi
2Mx16
2Mx16
2Mx16
2Mx16
32 16
x16
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
LCAS
Programming Register
LWCBR
Timing Register
DLL
CK,CK
LDMi
Data Strobe
CK,CK CKE CS RAS CAS WE LDM UDM
- 6 /19 -
Rev. 1.3 July 2007

6 Page



ページ 合計 : 18 ページ
 
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共有リンク

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部品番号部品説明メーカ
K4D261638K-LC40

128Mbit GDDR SDRAM

Samsung
Samsung


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