DataSheet.jp

CH7002D-V の電気的特性と機能

CH7002D-VのメーカーはETCです、この部品の機能は「Scalable VGA to NTSC/PAL Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 CH7002D-V
部品説明 Scalable VGA to NTSC/PAL Encoder
メーカ ETC
ロゴ ETC ロゴ 




このページの下部にプレビューとCH7002D-Vダウンロード(pdfファイル)リンクがあります。

Total 36 pages

No Preview Available !

CH7002D-V Datasheet, CH7002D-V PDF,ピン配置, 機能
CHRONTEL
CH7002D
Preliminary
Scalable VGA to NTSC/PAL Encoder
Features
• Fully integrated solution for PC to TV display
• TrueScale TM rendering engine supports underscan
operation for both 640x480 or 800x600 inputs
• Advanced 3-line digital flicker filtering with
programmable algorithm selections
• Fully programmable through I2C port or hardware
(pin-based) controls
• Wide range of VGA software drivers for full
synchronization and image positioning
• Auto-detection of TV presence
• Programmable power management features three
power-down modes
• Supports both NTSC and PAL (B, D, G, H, or I) TV
formats onto both composite and S-Video
• Triple 8-bit ADC inputs and triple 8-bit DAC outputs
• On-chip reference generation and loop filter
• Offered in 44-pin PLCC package
General Description
Chrontel’s CH7002 VGA to NTSC/PAL encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It accepts RGB analog inputs directly
from VGA controllers and converts them directly into NTSC
or PAL TV format, with simultaneous composite and
S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 8-
bit ADC and DAC interfaces, a 3-line vertical filter, and low-
jitter phase-locked loop to create outstanding quality video.
Through Chrontel’s TrueScale TM rendering technology, the
CH7002 supports full vertical and horizontal underscan
operation from either 640x480 or 800x600 input to either
NTSC or PAL outputs.
A high level of performance along with full programmability
makes the CH7002 ideal for system-level PC or Web
browser solutions. All features are software programmable,
through a standard I2C port, to enable fully integrated system
solutions by using a TV as the primary display device.
Patent number 5,781,241
PMODE
SD SC ADDR
I2C REGISTER & CONTROL
BLOCK
LINE
MEMORY
RSET
RSET
RR
ADC
Y
LINE RENDERING ENGINE
G
G COLOR
U
ADC
SPACE
-SCALING
CONVERTER
-DEFLICKERING
BB
V -SCAN CONVERSION
ADC
SYSTEM CLOCK
Y
U DIGITAL
NTSC/PAL
ENCODER
V & FILTER
DAC
DAC
DAC
VREF
PLL
TIMING & SYNC GENERATOR
OSC
VREF1 VREF2
XCLK
HV
Figure 1: Functional Block Diagram
XI XO
Y
CVBS
C
CLKOUT
201-0000-029 Rev 6.1, 8/2/99
1

1 Page





CH7002D-V pdf, ピン配列
CHRONTEL
CH7002D
Table 1. Pin Description
44-Pin
PLCC
Type
Symbol
2, 4, 6, 27,
39,42
Power
AGND
1, 3, 5
In B, G, R
7, 37, 40,
44
Power
AVDD
15 Out CLKOUT
8, 14, 33
Power
DVDD
10, 16, 31
Power
DGND
17 In XI
18 In XO/FIN
25
Power
VDD
26 In RSET
21
Power
GND
24 Out
Y
23 Out CVBS
Description
Analog ground
These pins provide the ground reference for the analog section of CH7002,
and MUST be connected to the system ground to prevent latchup. Refer to
the Application Information section for information on proper supply
decoupling.
VGA Inputs
These pins should be terminated with 75 ohm resistors and isolated from
switching digital signals and video output pins. Refer to the Application
Information section for detailed technical guidance and alternative connection
techniques.
Analog Supply Voltage
These pins supply the 5V power to the analog section of the CH7002. For
information on proper supply decoupling, refer to the Application Information
section.
Clock Output
This pin defaults to 14.31818 MHz upon power-up and remains active at all
times (including power-down).
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH7002. For
information on proper supply decoupling, refer to the Application Information
section.
Digital Ground
These pins provide the ground reference for the digital section of CH7002,
and MUST be connected to the system ground to prevent latchup. For
information on proper supply decoupling, refer to the Application Information
section.
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached
between XI and XO/FIN. However, if an external CMOS clock is attached to
XO/FIN, XI should be connected to ground.
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and
XI. An external CMOS compatible clock can be connected to XO/FIN as an
alternative.
DAC Power Supply
These pins supply power to CH7002’s internal DACs. Refer to the Application
Information section for information on proper supply decoupling.
Reference Resistor
A 324 resistor with short and wide traces should be attached between
RSET and ground. No other connections should be made to this pin.
DAC Ground
These pins provide the ground reference for CH7002’s internal DACs. For
information on proper supply decoupling, refer to the Application Information
section.
Luminance Output
A 75 termination resistor with short traces should be attached between Y
and ground for optimum performance. Use of additional filters is discussed in
the Application Information section.
Composite Output
A 75 termination resistor, with short traces, should be attached between
CVBS and ground for optimum performance. Use of additional filters is
discussed in the Application Information section.
201-0000-029 Rev 6.1, 8/2/99
3


3Pages


CH7002D-V 電子部品, 半導体
CHRONTEL
CH7002D
Functional Description
The CH7002 is a fully integrated system solution for converting analog RGB and synchronization signals from a
standard VGA source into high-quality NTSC or PAL video signals. This solution involves both hardware and
software elements, which work together, to produce an optimum TV screen image based on the original computer
generated pixel data. All essential circuitry for this conversion are integrated on chip. On-chip circuitry includes:
memory, memory control, scaling, PLL, ADC, DAC, filters, and a NTSC/PAL encoder. All internal signal
processing, including NTSC/PAL encoding, is performed using digital techniques, to ensure that the high-quality
video signals are not affected by drift issues associated with analog components. No additional adjustment is
required during manufacturing.
CH7002 is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support
components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation. The
CH7002 is designed to provide an ideal solution for computer motherboards, add-on graphics cards, TV-sets, and
scan converter boards.
Architectural Overview
The CH7002 is a complete TV output subsystem, using both hardware and software elements, to produce an image
on TV, that is virtually identical to the image that would be displayed on a monitor. Creating a compatible TV
output from a VGA input is a relatively straightforward process. This process includes a standard conversion from
RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, then encoding the
pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a
TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a
compatible TV output that displays a sharp and stable image of the right size, with minimal artifacts from the
conversion process.
As a key part of the overall system solution, the CH7002 software establishes the correct framework for the VGA
input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600),
the CH7002 software may be invoked to establish the appropriate TV output display. The software then programs
the various timing parameters of the VGA controller to create an output signal that will be compatible with the
chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates,
total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7002 can render
a superior TV image, without the added cost of a full frame buffer memory, normally used to implement features
such as scaling and full synchronization. Without this added system software, TV output solutions can only
guarantee compatible operation in VGA standard mode 12 (640x480x16 color, 60 Hz).
The CH7002 hardware accepts direct VGA outputs (analog RGB inputs), which are digitized on a pixel-by-pixel
basis by three 8-bit video A/D converters. The digitized RGB inputs are then color space converted into YUV in 4-
2-2 format (encoded into luminance (Y) and color-difference (U,V) signals) and stored in a line buffer memory.
The stored pixels are fed into a block where scan-rate conversion, underscan scaling, and 3-line vertical flicker
filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL
scan-rates; the vertical flicker filter eliminates flicker at the output, while the underscan scaling reduces the size of
the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to
minimize aliasing problems. The digital encoder receives the filtered signals and transforms the signals into
composite and S-Video outputs, which are converted by the three 8-bit DACs into analog outputs.
6 201-0000-029 Rev6.1, 8/2/99

6 Page



ページ 合計 : 36 ページ
 
PDF
ダウンロード
[ CH7002D-V データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
CH7002D-V

Scalable VGA to NTSC/PAL Encoder

ETC
ETC


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap