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EDI88128C の電気的特性と機能

EDI88128CのメーカーはWhite Electronic Designsです、この部品の機能は「128Kx8 MONOLITHIC SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 EDI88128C
部品説明 128Kx8 MONOLITHIC SRAM
メーカ White Electronic Designs
ロゴ White Electronic Designs ロゴ 




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EDI88128C Datasheet, EDI88128C PDF,ピン配置, 機能
White Electronic Designs
EDI88128C
128Kx8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
„ Access Times of 70, 85, 100ns
„ Available with Single Chip Selects (EDI88128) or
Dual Chip Selects (EDI88130)
„ 2V Data Retention (LP Versions)
„ CS# and OE# Functions for Bus Control
„ TTL Compatible Inputs and Outputs
„ Fully Static, No Clocks
„ Organized as 128Kx8
„ Industrial, Military and Commercial Temperature
Ranges
„ Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
„ Single +5V (±10%) Supply Operation
The EDI88128C is a high speed, high performance,
Monolithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an
additional chip select line (CS2) which will automatically
power down the device when proper logic levels are
applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simpliy decoding schemes in
memory banking where large multiple pages of memory
are required.
The EDI88128C and the EDI88130C have eight bi-
directional input-output lines to provide simultaneous
access to all bits in a word. An automatic power down
feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a
speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer
a 2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
Top View
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
AØ 12
I/OØ 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 NC/CS2*
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
PIN DESCRIPTION
I/O0-7
Data Inputs/Outputs
A0-16
Address Inputs
WE# Write Enable
CS1#, CS2
Chip Selects
OE# Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
1 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com

1 Page





EDI88128C pdf, ピン配列
White Electronic Designs
EDI88128C
AC Characteristics – Read Cycle
VCC = 5V, VSS = 0V, -55°C TA +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
Symbol
JEDEC
tAVAV
tAVQV
tELQV
tSHQV
tELQX
tSHQX
tEHQZ
tSLQZ
tAVQX
tGLQV
tGLQX
tGHQZ
Alt.
tRC
tAA
tACS
tACS
tCLZ
tCLZ
tCHZ
tCHZ
tOH
tOE
tOLZ
tOHZ
70ns
Min Max
70
70
70
70
3
3
30
30
3
25
0
0 30
85ns
Min Max
85
85
85
85
3
3
30
30
3
30
0
0 30
1. This parameter is guaranteed by design but not tested.
100ns
Min Max
100
100
100
100
3
3
30
30
3
50
0
0 30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Test Conditions
Figure 1
Q
255Ω
Figure 2
Vcc
480Ω
30pF
Q
255Ω
Vcc
480Ω
5pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VSS to 3.0V
5ns
1.5V
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
3 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com


3Pages


EDI88128C 電子部品, 半導体
White Electronic Designs
EDI88128C
DATA RETENTION CHARACTERISTICS (EDI88128LP & EDI88130LP ONLY)
-55°C TA +125°C
Characteristic
Low Power Version only
Symbol
Conditions
Min
Typ
Max
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
VDD
ICCDR
TCDR
TR
VDD = 2.0V
CS1# VDD -0.2V
VIN VDD -0.2V
or VIN 0.2V
2
0
TAVAV*
400
NOTE:
1. Parameter guaranteed by design, but not tested.
* Read Cycle Time
Units
V
μA
ns
ns
FIGURE 5 – DATA RETENTION – CS1# CONTROLLED
Vcc
CS1#
tCDR
Data Retention Mode
4.5V VDD 4.5V
CS1# VDD -0.2V
tR
DATA RETENTION, CS1# CONTROLLED
FIGURE 6 – DATA RETENTION — CS2 CONTROLLED
Vcc
CS2
tCDR
Data Retention Mode
4.5V VDD 4.5V
CS2 ≤ 0.2V
tR
DATA RETENTION, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
April 2005
Rev. 17
6 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com

6 Page



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部品番号部品説明メーカ
EDI88128C

128K X 8 STATIC RAM CMOS MONOLITHIC

ETC
ETC
EDI88128C

128Kx8 MONOLITHIC SRAM

White Electronic Designs
White Electronic Designs
EDI88128CS

128Kx8 Monolithic SRAM

White Electronic Designs
White Electronic Designs
EDI88128LP

128K X 8 STATIC RAM CMOS MONOLITHIC

ETC
ETC


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