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PDF 24C64A Data sheet ( Hoja de datos )
| Número de pieza | 24C64A | |
| Descripción | Two-Wire Serial EEPROM | |
| Fabricantes | Fremont Micro Devices | |
| Logotipo |  |
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Two-Wire Serial EEPROM
32K, 64K (8-bit wide)
24C32A, 24C64A
FEATURES
Low voltage and low power operations:
• FT24C32A/64A:
VCC = 1.8V to 5.5V
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).
32 bytes page write mode.
Partial page write operation allowed.
Internally organized: 4096 × 8 (32K), 8192 × 8 (64K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed Write Cycle (5ms maximum).
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1, 000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40o C to 85o C).
Standard 8-pin DIP/SOP/TSSOP/MSOP/DFN and 5-pin SOT23 Pb-free packages.
DESCRIPTION
The FT24C32A/64A series are 32768/65536 bits of serial Electrical Erasable and Programmable Read Only Memory,
commonly known as EEPROM. They are organized as 4096/8192 words of 8 bits (one byte) each. The devices are
fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are
available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead MSOP, 8-lead DFN, and 5-lead SOT23 packages.
A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to
5.5V) devices enables wide spectrum of applications.
PIN CONFIGURATION
Pin Name
A2, A1, A0
SDA
SCL
WP
NC
Pin Function
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
Write Protect
No-Connect
© 2009 Fremont Micro Devices Inc.
DS3005J-page1
1 page  
24C32A, 24C64A
WRITE OPERATIONS
(A) BYTE WRITE
A write operation requires two 8-bit data word address following the device address word and ACKNOWLEDGE
signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data
word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such
as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters
into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not
respond until the writing is completed (figure 3).
(B) PAGE WRITE
The 32K/64K EEPROM are capable of 32-byte page write.
A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition
after the first data word is clocked in. The microcontroller can transmit up to 31 more data words after the
EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word
is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 4).
The lower five bits of the data word address are internally incremented following the receipt of each data word.
The higher data word address bits are not incremented, retaining the memory page row location. If more than 32
data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be
overwritten.
(C) ACKNOWLEDGE POLLING
ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming.
By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the
device is still in the self-timed programming mode. However, if the programming completes and the chip has
returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle.
READ OPERATIONS
The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three
read operation modes are described as follows:
(A) CURRENT ADDRESS READ
The EEPROM internal address word counter maintains the last read or write address plus one if the power supply
to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a
START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response
with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out.
The internal address word counter will then automatically increase by one. For current address read the micro-
controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid
STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode
(see Figure 5).
(B) SEQUENTIAL READ
The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid
device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE
signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally
address word counter will then automatically increase by one.
© 2009 Fremont Micro Devices Inc.
DS3005J-page5
5 Page 
DIP8 PACKAGE OUTLINEDIMENSIONS
24C32A, 24C64A
Symbol
A
A1
A2
B
B1
C
D
E
E1
e
L
E2
Dimensions In Millimeters
Min Max
3.710
4.310
0.510
3.200
3.600
0.380
0.570
1.524（BSC）
0.204
0.360
9.000
9.400
6.200
6.600
7.320
7.920
2.540 (BSC)
3.000
3.600
8.400
9.000
Dimensions In Inches
Min Max
0.146
0.170
0.020
0.126
0.142
0.015
0.022
0.060（BSC）
0.008
0.014
0.354
0.370
0.244
0.260
0.288
0.312
0.100（BSC）
0.118
0.142
0.331
0.354
© 2009 Fremont Micro Devices Inc.
DS3005J-page11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 24C64A.PDF ] | |
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