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PDF ETA3560 Data sheet ( Hoja de datos )
| Número de pieza | ETA3560 | |
| Descripción | 1.5MHz Step-Down Converter | |
| Fabricantes | ETA | |
| Logotipo |  |
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ETA3560
1A, 1.5MHz Step-Down Converter in DFN2X2-6 Package
DESCRIPTION
The ETA3560 is a high-efficiency, DC-to-DC step-down
switching regulator, capable of delivering up to 1A of output
current. The devices operate from an input voltage range of
2.6V to 5.5V and provide output voltages from 0.6V to VIN,
making the ETA3560 ideal for low voltage power conversions.
Running at a fixed frequency of 1.5MHz allows the use of small
inductance value and low DCR inductors, thereby achieving
higher efficiencies. Other external components, such as
ceramic input and output caps, can also be small due to
higher switching frequency, while maintaining exceptional
low noise output voltages. Built-in EMI reduction circuitry
makes this converter ideal power supply for RF applications.
Internal soft-start control circuitry reduces inrush current.
Short-circuit and thermal-overload protection improves
design reliability.
ETA3560 is housed in a tiny DFN2X2-6L package
FEATURES
Up to 96% Efficiency
Up to 1A Max Output Current
1.5MHz Frequency
Light Load operation
Internal Compensation
Tiny DFN2X2-6L Package
APPLICATIONS
MIDs, Tablet PC
Set Top Boxes
USB ports/Hubs
Hot Swaps
Cellphones
ORDERING INFORMATION
PART #
PACKAGE PIN TOP MARK
ETA3560D2G DFN2X2-6 DIYW
TYPICAL APPLICATION
VIN 2.6V to 5.5V
4
IN
10μF 1
EN
GND
2
SW 3
FB 5
VOUT
1.8V/1A
2.2μH
100K
22pF Optional
10μF
50K
1.8V/1A 1.5MHz Step-Down Converter
100% Efficiency Vs IOUT
95%
90%
85%
80%
75%
70%
65%
60%
VIN=2.7V
55% VIN=3.6V
50%
45%
40%
VOUT=1.8V
VIN=5V
0.001 0.01
0.1
1
IOUT (A)
www.ETAsolution.com
Outperform with Efficiency
Proprietary Information DO NOT Distribute
1
1 page  
ETA3560
Current Sense
An internal current-sense amplifier senses the current through the high-side MOSFET during on time and produces a proportional
current signal, which is used to sum with the slope compensation signal. The summed signal then is compared with the error
amplifier output by the PWM comparator to terminate the on cycle.
Current Limit
There is a cycle-by-cycle current limit on the high-side MOSFET. When the current flowing out of SW exceeds this limit, the high-
side MOSFET turns off and the synchronous rectifier turns on. ETA3560 utilizes a frequency fold-back mode to prevent
overheating during short-circuit output conditions. The device enters frequency fold-back mode when the FB voltage drops below
200mV, limiting the current to IPEAK and reducing power dissipation. Normal operation resumes upon removal of the short-circuit
condition.
Soft-start
ETA3560 has an internal soft-start circuitry to reduce supply inrush current during startup conditions. When the device exits
under-voltage lockout (UVLO), shutdown mode, or restarts following a thermal-overload event, the l soft-start circuitry slowly
ramps up current available at SW.
UVLO and Thermal Shutdown
If IN drops below 2.4V, the UVLO circuit inhibits switching. Once IN rises above 2.6V, the UVLO clears, and the soft-start sequence
activates. Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds TJ=
+160°C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again
after the junction temperature cools by 15°C, resulting in a pulsed output during continuous overload conditions. Following a
thermal-shutdown condition, the soft-start sequence begins.
DESIGN PROCEDURE
Setting Output Voltages
Output voltages are set by external resistors. The FB threshold
is 0.6V.
RTOP = RBOTTOM x [(VOUT / 0.6) - 1]
Input Capacitor and Output Capacitor Selection
The input capacitor in a DC-to-DC converter reduces current
peaks drawn from the battery or other input power source and
reduces switching noise in the controller. The impedance of the
input capacitor at the switching frequency should be less than
that of the input source so high-frequency switching currents
do not pass through the input source. Input ripple with a
ceramic capacitor is approximately as follows:
VRIPPLE = IL(PEAK)[1 / (2π x fOSC x CIN)]
If the capacitor has significant ESR, the output ripple
component due to capacitor ESR is as follows:
VRIPPLE(ESR) = IL(PEAK) x ESR
The output capacitor keeps output ripple small and ensures
control-loop stability. The output capacitor must also have low
impedance at the switching frequency. Ceramic, polymer, and
tantalum capacitors are suitable, with ceramic exhibiting the
lowest ESR and high-frequency impedance.
Inductor Selection
A reasonable inductor value (LIDEAL) can be derived from the
following:
LIDEAL = [2(VIN) x D(1 - D)] / IOUT x fOSC
www.ETAsolution.com
Outperform with Efficiency
Proprietary Information DO NOT Distribute
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ETA3560.PDF ] | |
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