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PDF HWD2111 Data sheet ( Hoja de datos )
| Número de pieza | HWD2111 | |
| Descripción | Dual 105mW Headphone Amplifier | |
| Fabricantes | CSMSC | |
| Logotipo |  |
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HWD2111
Dual 105mW Headphone Amplifier with Digital Volume
Control and Shutdown Mode
General Description
Key Specifications
The HWD2111 is a dual audio power amplifier capable of n THD+N at 1kHz, 105mW continuous average output
delivering 105mW per channel of continuous average power
power into 16Ω
0.1% (typ)
into a 16Ω load with 0.1% (THD+N) from a 5V power supply. n THD+N at 1kHz, 70mW continuous average power into
audio power amplifiers were designed specifically to
32Ω
0.1% (typ)
provide high quality output power with a minimal amount of n Shutdown Current
external components. Since the HWD2111 does not require
0.3µA (typ)
bootstrap capacitors or snubber networks, it is optimally Features
suited for low-power portable systems.
n Digital volume control range from +12dB to −33dB
The HWD2111 features a digital volume control that sets the n LD and MSOP surface mount packaging
amplifier’s gain from +12dB to −33dB in 16 discrete steps
using a two−wire interface.
The unity-gain stable HWD2111 also features an externally
controlled, active-high, micropower consumption shutdown
n
n
n
"Click and Pop" suppression circuitry
No bootstrap capacitors required
Low shutdown current
mode. It also has an internal thermal shutdown protection
mechanism.
Applications
n Cellular Phones
n MP3, CD, DVD players
n PDA’s
n Portable electronics
Connection Diagrams
MSOP Package
LD Package
Top View
Order Number HWD2111MM
Top View
Order Number HWD2111LD
1
1 page  
Electrical Characteristics (Notes 1, 8) (Continued)
The following specifications apply for VDD = 2.6V unless otherwise specified, limits apply to TA = 25˚C.
Symbol
Parameter
Conditions
HWD2111
Typical
Limit
(Note 4) (Note 5)
Shutdown Attenuation
Shutdown mode active
−75
Units
(Limits)
dB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 4: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 5: Tested limits are guaranteed to CSMSC’s AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are guaranteed by design, test,
or statistical analysis.
Note 6: : Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50 Ohms).
Note 7: The LDA10A package has its Exposed−DAP soldered to an exposed 2in2 area of 1oz printed circuit board copper.
Note 8: All voltages are measured with respect to the ground pin, unless otherwise specified.
External Components Description
(Figure 1)
Components
1. Ci
2. CS
3. CB
4. CO
Functional Description
This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to, the
amplifier’s input terminals. Ci also creates a highpass filter with the internal input resistor, Ri, at fc =
1/(2πRiCi). The minimum value of Ri is 33kΩ. Refer to the section, Proper Selection of External
Components, for an explanation of how to determine the value of Ci.
This is the supply bypass capacitor. It provides power supply filtering. Refer to the Application
Information section for proper placement and selection of the supply bypass capacitor.
This is the BYPASS pin capacitor. It provides half-supply filtering. Refer to the section, Proper
Selection of External Components, for information concerning proper placement and selection of CB.
This is the output coupling capacitor. It blocks the DC voltage at the amplifier’s output and it forms a
high pass filter with RL at fO = 1/(2πR LCO)
Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
5
5 Page 
Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Frequency Response
Supply Current vs
Supply Voltage
Application Information
DIGITAL VOLUME CONTROL
The HWD2111’s gain is controlled by the signals applied to the
CLOCK and UP/DN inputs. An external clock is required to
drive the CLOCK pin. At each rising edge of the clock signal,
the gain will either increase or decrease by a 3dB step
depending on the logic voltage level applied to the UP/DN
pin. A logic high voltage level applied to the UP/DN pin
causes the gain to increase by 3dB at each rising edge of the
clock signal. Conversely, a logic low voltage level applied to
the UP/DN pin causes the gain to decrease 3dB at each
rising edge of the clock signal. For both the CLOCK and
UP/DN inputs, the trigger point is 1.4V minimum for a logic
high level, and 0.4V maximum for a logic low level.
There are 16 discrete gain settings ranging from +12dB
maximum to −33dB minimum. Upon device power on, the
amplifier’s gain is set to a default value of 0dB. However,
when coming out of shutdown mode, the HWD2111 will revert
back to its previous gain setting.
The HWD2111’s CLOCK and UP/DN pins should be de-
bounced in order to avoid unwanted state changes during
transitions between VIL and VIH. This will ensure correct
operation of the digital volume control. A microcontroller or
microprocessor output is recommended to drive the CLOCK
and UP/DN pins.
FIGURE 2. Timing Diagram
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet HWD2111.PDF ] | |
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