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PDF IS42VS16400E Data sheet ( Hoja de datos )
| Número de pieza | IS42VS16400E | |
| Descripción | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS42VS16400E
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
MAY 2009
FEATURES
• Clock frequency: 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVCMOS interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Packages:
400-mil 54-pin TSOP II
54-ball TF-BGA (8mm x 8mm)
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42VS16400E is
organized as 1,048,576 bits x 16-bit x 4-bank for improved
performance.The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 GND
53 DQ15
52 GNDQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 GNDQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 GND
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 GND
PIN DESCRIPTIONS
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
CS
RAS
CAS
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
VDD
GND
VDDq
GNDq
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/15/09
1
1 page  
IS42VS16400E
Function (In Detail)
A0-A11 are address inputs sampled during the ACTIVE
(row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto PRECHARGE). A10 is sampled during
a PRECHARGE command to determine if all banks are to
be PRECHARGED (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Bank Select Address (BA0 and BA1) defines which bank
the ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
CAS, in conjunction with the RAS and WE, forms the device
command. See the “Command Truth Table” for details on
device commands.
The CKE input determines whether the CLK input is en-
abled. The next rising edge of the CLK signal will be valid
when is CKE HIGH and invalid when LOW. When CKE is
LOW, the device will be in either power-down mode, CLOCK
SUSPEND mode, or SELF-REFRESH mode. CKE is an
asynchronous input.
CLK is the master clock input for this device. Except for
CKE, all inputs to this device are acquired in synchroniza-
tion with the rising edge of this pin.
The CS input determines whether command input is en-
abled within the device. Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH. DQ0 to
DQ15 are DQ pins.DQ through these pins can be controlled
in byte units using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of
the DQ buffers. In read mode, LDQM and UDQM control
the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH,
disabled. The outputs go to the HIGH Impedance State
when LDQM/UDQM is HIGH. This function corresponds
to OE in conventional DRAMs. In write mode, LDQM and
UDQM control the input buffer. When LDQM or UDQM is
LOW, the corresponding buffer byte is enabled, and data
can be written to the device. When LDQM or UDQM is
HIGH, input data is masked and cannot be written to the
device.
RAS, in conjunction with CAS and WE , forms the device
command. See the “Command Truth Table” item for details
on device commands.
WE , in conjunction with RAS and CAS , forms the device
command. See the “Command Truth Table” item for details
on device commands.
VDDq is the output buffer power supply.
VDD is the device internal power supply.
GNDq is the output buffer ground.
GND is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/15/09
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A7 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bisatnhkesp(se)riiosdexreeqcuutireeddaffoter rbpaanskspargeechoaf rtghienpge. r OiondctReP,awbhainchk
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the pre-
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
requiring an explicit command. A10 to enables the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
5
5 Page 
IS42VS16400E
TRUTH TABLE – CURRENT STATE BANK COMMAND TO BANK (1-6)
CURRENT STATE COMMAND (ACTION)
CS RAS CAS WE
Any
COMMAND INHIBIT (NOP/Continue previous operation)
H X X X
NO OPERATION (NOP/Continue previous operation)
L H H H
Idle Any Command Otherwise Allowed to Bank m
X X X X
Row
ACTIVE (Select and activate row)
L L H H
Activating,
READ (Select column and start READ burst)(7)
L H L H
Active, or
WRITE (Select column and start WRITE burst)(7)
L H L L
Precharging
PRECHARGE
L L H L
Read
ACTIVE (Select and activate row)
L L H H
(Auto
READ (Select column and start new READ burst)(7,10)
L H L H
Precharge
WRITE (Select column and start WRITE burst)(7,11)
L H L L
Disabled)
PRECHARGE(9)
L L H L
Write
ACTIVE (Select and activate row)
L L H H
(Auto
READ (Select column and start READ burst)(7,12)
L H L H
Precharge
WRITE (Select column and start new WRITE burst)(7,13)
L H L L
Disabled)
PRECHARGE(9)
L L H L
Read
ACTIVE (Select and activate row)
L L H H
(With Auto
READ (Select column and start new READ burst)(7,8,14)
L H L H
Precharge)
WRITE (Select column and start WRITE burst)(7,8,15)
L H L L
PRECHARGE(9)
L L H L
Write
ACTIVE (Select and activate row)
L L H H
(With Auto
READ (Select column and start READ burst)(7,8,16)
L H L H
Precharge)
WRITE (Select column and start new WRITE burst)(7,8,17)
L H L L
PRECHARGE(9)
L L H L
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after txsr has been met (if the previ-
ous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-
tions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and trp has been met.
Row Active: A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/15/09
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS42VS16400E.PDF ] | |
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