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IS42VS16100E PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS42VS16100E
部品説明 16Mb SYNCHRONOUS DYNAMIC RAM
メーカ ISSI
ロゴ ISSI ロゴ 



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IS42VS16100E Datasheet, IS42VS16100E PDF,ピン配置, 機能
IS42VS16100E
512K Words x 16 Bits x 2 Banks
16Mb SYNCHRONOUS DYNAMIC RAM
PRELIMINARY INFORMATION
FEBRUARY 2011
FEATURES
• Clock frequency: 133, 100, 83 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II and 60-ball
BGA
• Lead-free package option
• Auto refresh and self-refresh modes
• Power down and deep power down
PIN DESCRIPTIONS
A0-A11
Address Input
A0-A10
Row Address Input
A11
Bank Select Address
A0-A7
Column Address Input
DQ0 to DQ15 Data DQ
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42VS16100E is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VDDQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
RAS
CAS
WE
LDQM
UDQM
VDD
VSS
VDDQ
VSSQ
NC
Row Address Strobe Command
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00E
01/21/2011
1

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