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IS42SM32160C の電気的特性と機能

IS42SM32160CのメーカーはISSIです、この部品の機能は「512Mb Mobile Synchronous DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS42SM32160C
部品説明 512Mb Mobile Synchronous DRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS42SM32160C Datasheet, IS42SM32160C PDF,ピン配置, 機能
IS42SM32160C
IS42RM32160C
16Mx32
512Mb Mobile Synchronous DRAM
NOVEMBER 2010
FEATURES:
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access and pre-
charge
• Programmable CAS latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, and Full
Page
• Programmable Burst Sequence:
• Sequential and Interleave
• Auto Refresh (CBR)
• TCSR (Temperature Compensated Self Refresh)
• PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode (DPD)
• Driver Strength Control (DS): 1/4, 1/2, and Full
OPTIONS:
• Configuration: 16Mx32
• Power Supply:
IS42SMxxx - Vdd/Vddq = 3.3V
IS42RMxxx - Vdd/Vddq = 2.5V
• Package: 90 Ball BGA (8x13mm)
• Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
• Die revision: C
DESCRIPTION:
ISSI's IS42SM/RM32160C is a 512Mb Mobile Syn-
chronous DRAM configured as a quad 4M x32 DRAM.
It achieves high-speed data transfer using a pipeline
architecture with a synchronous interface. All inputs and
outputs signals are registered on the rising edge of the
clock input, CLK. The 512Mb SDRAM is internally con-
figured by stacking two 256Mb, 16Mx16 devices. Each
of the 4M x32 banks is organized as 8192 rows by 512
columns by 32 bits.
KEY TIMING PARAMETERS
Parameter
-7 -75
CLK Cycle Time
CAS Latency = 3
7 7.5
CAS Latency = 2
9.6 9.6
CLK Frequency
CAS Latency = 3
143 133
CAS Latency = 2
104 104
Access Time from CLK
CAS Latency = 3
5.4 5.4
CAS Latency = 2
77
Unit
ns
ns
Mhz
Mhz
ns
ns
ADDRESS TABLE
Parameter
Configuration
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
16Mx32
4M x 32 x 4 banks
BA0, BA1
A10/AP
A0 – A12
A0 – A8
8K / 64ms
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev.  A
11/09/2010
1

1 Page





IS42SM32160C pdf, ピン配列
IS42SM32160C
IS42RM32160C
PIN DESCRIPTIONS
Symbol
CLK
CKE
BA0, BA1
A0-A12
Type
Input
Input
Input
Input
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously
with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE
becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
Address Inputs:A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/
Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location in the
respective bank.During a Precharge command,A10 is sampled to determine if all banks are to be precharged
(A10 =HIGH).
CS
RAS
CAS
WE
DQM0-3
DQ0-31
Input
Input
Input
Input
Input
Input/
Output
The address inputs also provide the op-code during a Mode Register Set .
Chip Select:CS enables (sampled LOW) and disables (sampled HIGH) the command decoder.All commands
are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple
banks. It is considered part of the command code.
Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and
WE signals and is latched at the positive edges of CLK. When RAS and CS are asserted “LOW” and CAS
is asserted “HIGH,” either the BankActivate command or the Precharge command is selected by the WE
signal. When the WE is asserted “HIGH,” the BankActivate command is selected and the bank designated
by BA is turned on to the active state. When the WE is asserted “LOW,” the Precharge command is selected
and the bank designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS
and WE signals and is latched at the positive edges of CLK. When RAS is held “HIGH” and CS is asserted
“LOW,” the column access is started by asserting CAS ”LOW.” Then, the Read or Write command is selected
by asserting WE “LOW” or “HIGH.”
Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals
and is latched at the positive edges of CLK. The WE input is used to select the BankActivate or Precharge
command and Read or Write command.
Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers
are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled
HIGH during a write cycle. Output data is masked (two-clock latency) when DQM is sampled HIGH during
a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0
Data I/O: The DQ0-31 input and output data are synchronized with the positive edge of CLK. The I/Os are
byte-maskable during Reads and Writes.
Integrated Silicon Solution, Inc.
Rev.  A
11/09/2010
3


3Pages


IS42SM32160C 電子部品, 半導体
IS42SM32160C
IS42RM32160C
MODE REGISTER DEFINITION
BA1
0
0
1
1
BA0
0
1
0
1
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0 Address Bus (Ax)
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
000
001
010
011
100
101
110
111
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3 Type
0 Sequential
1 Interleaved
Latency Mode
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7
00
——
M6-M0
Defined
Mode
Standard Operation
All Other States Reserved
Mode Register Definition
Program Mode Register
Reserved
Program Extended Mode Register
Reserved
Write Burst Mode
M9 Mode
0 Programmed Burst Length
1 Single Location Access
To ensure compatibility with future devices,
should program A12, A11, A10 = "0"
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x32) when the burst length is set to two; by A2-A8 (x32) when the
burst length is set to four; and by A3-A8 (x32) when the burst length is set to eight. The remaining (least significant)
address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached.
6 Integrated Silicon Solution, Inc.
Rev.  A
11/09/2010

6 Page



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共有リンク

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部品番号部品説明メーカ
IS42SM32160C

512Mb Mobile Synchronous DRAM

ISSI
ISSI
IS42SM32160E

4M x 32Bits x 4Banks Mobile Synchronous DRAM

ISSI
ISSI


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