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PDF IS45S32800G Data sheet ( Hoja de datos )
| Número de pieza | IS45S32800G | |
| Descripción | 256Mb SYNCHRONOUS DRAM | |
| Fabricantes | ISSI | |
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IS42S32800G
IS45S32800G
8M x 32
256Mb SYNCHRONOUS DRAM
AUGUST 2012
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 4096 refresh cycles every 16ms (A2 grade) or
64 ms (Commercial, Industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
90-ball TF-BGA
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade, A1 (-40oC to +85oC)
Automotive Grade, A2 (-40oC to +105oC)
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized in 2Meg x 32 bit x 4
Banks.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5
5
10
200
100
4.8
6.5
-6 -7 Unit
6 7 ns
10 7.5 ns
166 143 Mhz
100 133 Mhz
5.4 5.4 ns
6.5 5.5 ns
ADDRESS TABLE
Parameter
Configuration
Refresh Count Com./Ind.
A1
A2
Row Addresses
Column
Addresses
Bank Address
Pins
Autoprecharge
Pins
8M x 32
2M x 32 x 4 banks
4K / 64ms
4K / 64ms
4K / 16ms
A0 – A11
A0 – A8
BA0, BA1
A10/AP
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. - www.issi.com 1
Rev. A
07/18/2012
1 page  
IS42S32800G, IS45S32800G
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A8 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A8. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bisatnhke(sp)eirsioedxerecquuteirdedafftoerrbpaansksapgreecohfatrhgeinpge. r iOodnctReP,awbhainchk
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the pre-
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
requiring an explicit command. A10 to enable the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(trc) is
required for a single refresh operation, and no other com-
mands can be executed during this period. This command
is executed at least 4096 times for every Tref. During an
AUTO REFRESH command, address bits are “Don’t Care”.
This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
5 Integrated Silicon Solution, Inc. - www.issi.com
Rev. A
07/18/2012
5 Page 
IS42S32800G, IS45S32800G
CKE RELATED COMMAND TRUTH TABLE(1)
Current State
Operation
CKE
n-1 n CS RAS CAS WE Address
Self-Refresh (S.R.) INVALID, CLK (n - 1) would exit S.R.
H X X
X X X X
Self-Refresh Recovery(2)
L H H
X X X X
Self-Refresh Recovery(2)
L H L
H H X X
Illegal
L H L
H L X X
Illegal
L H L
L X X X
Maintain S.R.
L L X
X X X X
Self-Refresh Recovery Idle After trc
H H H
X X X X
Idle After trc
H H L
H H X X
Illegal
H H L
H L X X
Illegal
H H L
L X X X
Begin clock suspend next cycle(5)
H L H
X X X X
Begin clock suspend next cycle(5)
H L L
H H X X
Illegal
H L L
H L X X
Illegal
H L L
L X X X
Exit clock suspend next cycle(2)
L H X
X X X X
Maintain clock suspend
L L X
X X X X
Power-Down (P.D.) INVALID, CLK (n - 1) would exit P.D.
H X X
X X X —
EXIT P.D. --> Idle(2)
L H X
X X X X
Maintain power down mode
L L X
X X X X
Both Banks Idle Refer to operations in Operative Command Table H H H
X X X —
Refer to operations in Operative Command Table H H L
H X X —
Refer to operations in Operative Command Table H H L
L H X —
Auto-Refresh
H H L
L L H X
Refer to operations in Operative Command Table H H L
L L L Op - Code
Refer to operations in Operative Command Table H L H
X X X —
Refer to operations in Operative Command Table H L L
H X X —
Refer to operations in Operative Command Table H L L
L H X —
Self-Refresh(3)
H L L L L H X
Refer to operations in Operative Command Table H L L
L L L Op - Code
Power-Down(3)
L X X X X X X
Any state
Refer to operations in Operative Command Table H H X
X X X X
other than
Begin clock suspend next cycle(4)
H L X
X X X X
listed above
Exit clock suspend next cycle
L H X
X X X X
Maintain clock suspend
L L X
X X X X
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if txsr is not satisfied.
11 Integrated Silicon Solution, Inc. - www.issi.com
Rev. A
07/18/2012
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS45S32800G.PDF ] | |
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